Microprocessor

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Microprocessor – Overwatch

Microprocessor is a manageling device of a micro-computer, fabricated on a small chip capable of performing ALU (Arithmetic Logical Unit) operations and communicating with the other devices connected to it.

Microprocessor consists of an ALU, register array, and a manage device. ALU performs arithmetical and logical operations on the data received from the memory or an input device. Register array consists of registers identified simply simply by permitters like B, C, D, E, H, L and accumulator. The manage device manages the flow of data and instructions wislim the computer.

Block Diagram of a Basic Microcomputer

Basic Microcomputer

How does a Microprocessor Work?

The microprocessor follows a sequence: Fetch, Decode, and then Execute.

Initially, the instructions are stored-coloureddish in the memory in a sequential order. The microprocessor fetches those instructions from the memory, then decodes it and executes those instructions till STOP instruction is reveryed. Later, it sends the result in binary to the out generally appropriate now thereput port. Between these processes, the register stores the temporarily data and ALU performs the computing functions.

List of Terms Used in a Microprocessor

Here is a list of a few of the regularly used terms in a microprocessor −

  • Instruction Set − It is the set of instructions tmind put on the microprocessor can belowstand.

  • Bandwidth − It is the numend up beingr of bit is processed in a performle instruction.

  • Clock Speed − It figure outs the numend up beingr of operations per second the processor can perform. It is expressed in megahertz (MHz) or gigahertz (GHz).It is furthermore belowstandn as Clock Rate.

  • Word Length − It depends upon the width of internal data bus, registers, ALU, etc. An 8-bit microprocessor can process 8-bit data at a time. The word size ranges from 4 bit is to 64 bit is depending upon the kind of the microcomputer.

  • Data Types − The microprocessor has multiple data kind formats like binary, BCD, ASCII, signed and unsigned numend up beingrs.

Features of a Microprocessor

Here is a list of a few of the many prominent features of any microprocessor −

  • Cost-effective − The microprocessor chips are available at low prices and results it is low cost.

  • Size − The microprocessor is of small dimension chip, hence is portable.

  • Low Power Consumption − Microprocessors are manufbehaveured-coloureddish simply simply by uperform metallicoxide semiconductor technology, which has low power consumption.

  • Versatility − The microprocessors are versatile as we can use the exbehave exact same chip in a numend up beingr of applications simply simply by configuring the delicateware program.

  • Relicapacity − The failure rate of an IC in microprocessors is very low, hence it is reliable.

Microprocessor – Classification

A microprocessor can end up being courseified into 3 categories −

Classification of Microprocessor

RISC Processor

RISC stands for Reduced Instruction Set Computer. It is styleed to red-coloureddishuce the execution time simply simply by simplifying the instruction set of the computer. Uperform RISC processors, every instruction requires only one clock cycle to execute results in uniform execution time. This red-coloureddishuces the efficiency as generally appropriate now there are more seriess of code, hence more RAM is needed to store the instructions. The compiler furthermore has to work more to convert high-level language instructions into machine code.

Some of the RISC processors are −

  • Power PC: 601, 604, 615, 620
  • DEC Alpha: 210642, 211066, 21068, 21164
  • MIPS: TS (R10000) RISC Processor
  • PA-RISC: HP 7100LC

Architecture of RISC

RISC microprocessor architecture uses highly-optimized set of instructions. It is used in portable devices like Apple iPod because of to it is power efficiency.

Architecture of RISC

Charbehaveeristics of RISC

The major charbehaveeristics of a RISC processor are as follows −

  • It consists of easy instructions.

  • It supports various data-kind formats.

  • It utilizes easy addresperform modes and fixed size instructions for pipelining.

  • It supports register to use in any context.

  • One cycle execution time.

  • “LOAD” and “STORE” instructions are used to access the memory location.

  • It consists of huger numend up beingr of registers.

  • It consists of less numend up beingr of transistors.

CISC Processor

CISC stands for Complex Instruction Set Computer. It is styleed to minimise the numend up beingr of instructions per program, ignoring the numend up beingr of cycles per instruction. The emphasis is on constructing complex instructions immediately into the hardware.

The compiler has to do very small work to translate a high-level language into assembly level language/machine code end up beingcause the size of the code is relatively short, so very small RAM is required-coloureddish to store the instructions.

Some of the CISC Processors are −

  • IBM 370/168
  • VAX 11/780
  • Intel 80486

Architecture of CISC

It’s architecture is styleed to decrreare locatedve the memory cost end up beingcause more storage is needed in huger programs resulting in higher memory cost. To resolve this particular particular, the numend up beingr of instructions per program can end up being red-coloureddishuced simply simply by emend up beingdding the numend up beingr of operations in a performle instruction.

Architecture of CISC

Charbehaveeristics of CISC

  • Variety of addresperform modes.
  • Larger numend up beingr of instructions.
  • Variable size of instruction formats.
  • Several cycles may end up being required-coloureddish to execute one instruction.
  • Instruction-decoding logic is complex.
  • One instruction is required-coloureddish to support multiple addresperform modes.

Special Processors

These are the processors which are styleed for a few special purposes. Few of the special processors are briefly discussed −

Coprocessor

A coprocessor is a specially styleed microprocessor, which can handle it is particular function many times quicker than the regular microprocessor.

For example − Math Coprocessor.

Some Intel math-coprocessors are −

  • 8087-used with 8086
  • 80287-used with 80286
  • 80387-used with 80386

Input/Output Processor

It is a specially styleed microprocessor having a local memory of it is own, which is used to manage I/O devices with minimum CPU involvement.

For example

  • DMA (immediate Memory Access) manageler
  • Keypanel/mouse manageler
  • Graphic display manageler
  • SCSI port manageler

Transputer (Transistor Computer)

A transputer is a specially styleed microprocessor with it is own local memory and having links to connect one transputer to one more transputer for inter-processor communications. It was 1st styleed in 1980 simply simply by Inmos and is targeted to the utilization of VLSI technology.

A transputer can end up being used as a performle processor system or can end up being connected to external links, which red-coloureddishuces the construction cost and incrreare locatedves the performance.

For example − 16-bit T212, 32-bit T425, the floating stage (T800, T805 & T9000) processors.

DSP (Digital Signal Processor)

This processor is specially styleed to process the analog signals into a digital form. This is done simply simply by sampling the voltage level at regular time intervals and converting the voltage at tmind put on immediate into a digital form. This process is performed simply simply by a circuit caldirected an analogue to digital converter, A to D converter or ADC.

A DSP contains the folloearng components −

  • Program Memory − It stores the programs tmind put on DSP will use to process data.

  • Data Memory − It stores the information to end up being processed.

  • Compute Engine − It performs the maall of all of thematical procesperform, accesperform the program from the program memory and the data from the data memory.

  • Input/Output − It connects to the out generally appropriate now there’aspect world.

It’s applications are −

  • Sound and music synthesis
  • Audio and video compression
  • Video signal procesperform
  • 2D and 3d graphics acceleration.

For example − Texas Instrument’s TMS 320 series, e.g., TMS 320C40, TMS320C50.

Microprocessor – 8085 Architecture

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor styleed simply simply by Intel in 1977 uperform NMOS technology.

It has the folloearng configuration −

  • 8-bit data bus
  • 16-bit adgown bus, which can adgown upto 64KB
  • A 16-bit program counter
  • A 16-bit stack stageer
  • Six 8-bit registers arranged in pairs: BC, DE, HL
  • Requires +5V supply to operate at 3.2 MHZ performle phase clock

It is used in washing machines, micseriesave ovens, mobile phones, etc.

8085 Microprocessor – Functional Unit is

8085 consists of the folloearng functional device’s −

Accumulator

It is an 8-bit register used to perform arithmetic, logical, I/O & LOAD/STORE operations. It is connected to internal data bus & ALU.

Arithmetic and logic device

As the name suggests, it performs arithmetic and logical operations like Addition, Subtrbehaveion, AND, OR, etc. on 8-bit data.

General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H & L. Each register can hold 8-bit data.

These registers can work in pair to hold 16-bit data and their particular own pairing combination is like B-C, D-E & H-L.

Program counter

It is a 16-bit register used to store the memory adgown location of the next instruction to end up being executed. Microprocessor increments the program whenever an instruction is end up beinging executed, so tmind put on the program counter stages to the memory adgown of the next instruction tmind put on is going to end up being executed.

Stack stageer

It is furthermore a 16-bit register works like stack, which is always incremented/decremented simply simply by 2 during push & pop operations.

Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

Flag register

It is an 8-bit register having five 1-bit flip-flops, which holds possibly 0 or 1 depending upon the result stored-coloureddish in the accumulator.

These are the set of 5 flip-flops −

  • Sign (S)
  • Zero (Z)
  • Auxiliary Carry (AC)
  • Parity (P)
  • Carry (C)

It’s bit position is shown in the folloearng table −

D7 D6 D5 D4 D3 D2 D1 D0
S Z AC P CY

Instruction register and decoder

It is an 8-bit register. When an instruction is fetched from memory then it is stored-coloureddish in the Instruction register. Instruction decoder decodes the information present in the Instruction register.

Timing and manage device

It provides timing and manage signal to the microprocessor to perform operations. Folloearng are the timing and manage signals, which manage external and internal circuit is −

  • Control Signals: READY, RD’, WR’, ALE
  • Status Signals: S0, S1, IO/M’
  • DMA Signals: HOLD, HLDA
  • RESET Signals: RESET IN, RESET OUT

Interrupt manage

As the name suggests it manages the interrupts during a process. When a microprocessor is executing a main program and whenever an interrupt occurs, the microprocessor shifts the manage from the main program to process the incoming request. After the request is comppermited, the manage goes back to the main program.

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5, TRAP.

Serial Input/out generally appropriate now thereput manage

It manages the serial data communication simply simply by uperform these two instructions: SID (Serial input data) and SOD (Serial out generally appropriate now thereput data).

Adgown buffer and adgown-data buffer

The content stored-coloureddish in the stack stageer and program counter is loaded into the adgown buffer and adgown-data buffer to communicate with the CPU. The memory and I/O chips are connected to these buses; the CPU can exalter the desired-coloureddish data with the memory and I/O chips.

Adgown bus and data bus

Data bus carries the data to end up being stored-coloureddish. It is biimmediateional, whereas adgown bus carries the location to where it need to end up being stored-coloureddish and it is uniimmediateional. It is used to transfer the data & Adgown I/O devices.

8085 Architecture

We have tried to depict the architecture of 8085 with this particular particular folloearng image −

8085 Architecture

Microprocessor – 8085 Pin Configuration

The folloearng image depicts the pin diagram of 8085 Microprocessor −

8085 Pin Configuration

The pins of a 8085 microprocessor can end up being courseified into sbehaveually groups −

Adgown bus

A15-A8, it carries the many significan not 8-bit is of memory/IO adgown.

Data bus

AD7-AD0, it carries the minimumern significan not 8-bit adgown and data bus.

Control and status signals

These signals are used to identify the nature of operation. There are 3 manage signal and 3 status signals.

Three manage signals are RD, WR & ALE.

  • RD − This signal indicates tmind put on the selected IO or memory device is to end up being read and is ready for accepting data available on the data bus.

  • WR − This signal indicates tmind put on the data on the data bus is to end up being produced into a selected memory or IO location.

  • ALE − It is a positive going pulse generated when a brand new operation is started simply simply by the microprocessor. When the pulse goes high, it indicates adgown. When the pulse goes down it indicates data.

Three status signals are IO/M, S0 & S1.

IO/M

This signal is used to variousiate end up beingtween IO and Memory operations, i.e. when it is high indicates IO operation and when it is low then it indicates memory operation.

S1 & S0

These signals are used to identify the kind of current operation.

Power supply

There are 2 power supply signals − VCC & VSS. VCC indicates +5v power supply and VSS indicates ground signal.

Clock signals

There are 3 clock signals, i.e. X1, X2, CLK OUT.

  • X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set frequency of the internal clock generator. This frequency is withinternally divided simply simply by 2.

  • CLK OUT − This signal is used as the system clock for devices connected with the microprocessor.

Interrupts & externally initiated signals

Interrupts are the signals generated simply simply by external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will discuss interrupts in detail in interrupts section.

  • INTA − It is an interrupt acbelowstanddirectedgment signal.

  • RESET IN − This signal is used to reset the microprocessor simply simply by setting the program counter to zero.

  • RESET OUT − This signal is used to reset all the connected devices when the microprocessor is reset.

  • READY − This signal indicates tmind put on the device is ready to send or receive data. If READY is low, then the CPU has to wait around for READY to go high.

  • HOLD − This signal indicates tmind put on one more master is requesting the use of the adgown and data buses.

  • HLDA (HOLD Acbelowstandladvantage) − It indicates tmind put on the CPU has received the HOLD request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the HOLD signal is removed.

Serial I/O signals

There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.

  • SOD (Serial out generally appropriate now thereput data series) − The out generally appropriate now thereput SOD is set/reset as specified simply simply by the SIM instruction.

  • SID (Serial input data series) − The data on this particular particular series is loaded into accumulator whenever a RIM instruction is executed.

8085 Addresperform Modes & Interrupts

Now permit us discuss the addresperform modes in 8085 Microprocessor.

Addresperform Modes in 8085

These are the instructions used to transfer the data from one register to one more register, from the memory to the register, and from the register to the memory without generally appropriate now there any alteration in the content. Addresperform modes in 8085 is courseified into 5 groups −

Immediate addresperform mode

In this particular particular mode, the 8/16-bit data is specified in the instruction it iself as one of it is operand. For example: MVI K, 20F: means 20F is copied into register K.

Register addresperform mode

In this particular particular mode, the data is copied from one register to one more. For example: MOV K, B: means data in register B is copied to register K.

Direct addresperform mode

In this particular particular mode, the data is immediately copied from the given adgown to the register. For example: LDB 5000K: means the data at adgown 5000K is copied to register B.

Inimmediate addresperform mode

In this particular particular mode, the data is transferred-coloureddish from one register to one more simply simply by uperform the adgown stageed simply simply by the register. For example: MOV K, B: means data is transferred-coloureddish from the memory adgown stageed simply simply by the register to the register K.

Implayd addresperform mode

This mode doesn’t require any operand; the data is specified simply simply by the opcode it iself. For example: CMP.

Interrupts in 8085

Interrupts are the signals generated simply simply by the external devices to request the microprocessor to perform a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR.

Interrupt are courseified into folloearng groups based on their particular own parameter −

  • Vector interrupt − In this particular particular kind of interrupt, the interrupt adgown is belowstandn to the processor. For example: RST7.5, RST6.5, RST5.5, TRAP.

  • Non-Vector interrupt − In this particular particular kind of interrupt, the interrupt adgown is not belowstandn to the processor so, the interrupt adgown needs to end up being sent externally simply simply by the device to perform interrupts. For example: INTR.

  • Maskable interrupt − In this particular particular kind of interrupt, we can disable the interrupt simply simply by writing a few instructions into the program. For example: RST7.5, RST6.5, RST5.5.

  • Non-Maskable interrupt − In this particular particular kind of interrupt, we cannot disable the interrupt simply simply by writing a few instructions into the program. For example: TRAP.

  • Software interrupt − In this particular particular kind of interrupt, the programmer has to add the instructions into the program to execute the interrupt. There are 8 delicateware interrupts in 8085, i.e. RST0, RST1, RST2, RST3, RST4, RST5, RST6, and RST7.

  • Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e. TRAP, RST7.5, RST6.5, RST5.5, INTA.

Note − NTA is not an interrupt, it is used simply simply by the microprocessor for sending acbelowstandladvantagement. TRAP has the highest priority, then RST7.5 and so on.

Interrupt Service Rout generally appropriate now thereine (ISR)

A small program or a rout generally appropriate now thereine tmind put on when executed, services the corresponding interrupting source is caldirected an ISR.

TRAP

It is a non-maskable interrupt, having the highest priority among all interrupts. Bydefault, it is enabdirected until it gets acbelowstandladvantaged. In case of failure, it executes as ISR and sends the data to backup memory. This withinterrupt transfers the manage to the location 0024H.

RST7.5

It is a maskable interrupt, having the second highest priority among all interrupts. When this particular particular interrupt is executed, the processor saves the content of the PC register into the stack and branches to 003CH adgown.

RST 6.5

It is a maskable interrupt, having the third highest priority among all interrupts. When this particular particular interrupt is executed, the processor saves the content of the PC register into the stack and branches to 0034H adgown.

RST 5.5

It is a maskable interrupt. When this particular particular interrupt is executed, the processor saves the content of the PC register into the stack and branches to 002CH adgown.

INTR

It is a maskable interrupt, having the lowest priority among all interrupts. It can end up being disabdirected simply simply by resetting the microprocessor.

When INTR signal goes high, the folloearng behaveuallyts can occur −

  • The microprocessor checks the status of INTR signal during the execution of every instruction.

  • When the INTR signal is high, then the microprocessor comppermites it is current instruction and sends behaveive low interrupt acbelowstandladvantage signal.

  • When instructions are received, then the microprocessor saves the adgown of the next instruction on stack and executes the received instruction.

Microprocessor – 8085 Instruction Sets

Let us get a look at the programming of 8085 Microprocessor.

Instruction sets are instruction codes to perform a few task. It is courseified into five categories.

S.No. Instruction & Description
1 Control Instructions

Folloearng is the table footweararng the list of Control instructions with their particular own meanings.

2 Logical Instructions

Folloearng is the table footweararng the list of Logical instructions with their particular own meanings.

3 Branching Instructions

Folloearng is the table footweararng the list of Branching instructions with their particular own meanings.

4 Arithmetic Instructions

Folloearng is the table footweararng the list of Arithmetic instructions with their particular own meanings.

5 Data Transfer Instructions

Folloearng is the table footweararng the list of Data-transfer instructions with their particular own meanings.

8085 – Demo Programs

Now, permit us get a look at a few program demonstrations uperform the above instructions −

Adding Two 8-bit Numend up beingrs

Write a program to add data at 3005H & 3006H memory location and store the result at 3007H memory location.

Problem demo

(3005H) = 14H 
   (3006H) = 89H

Result

14H + 89H = 9DH

The program code can end up being produced like this particular particular −

LXI H 3005H   : "HL stages 3005H" 
MOV A, M      : "Getting 1st operand" 
INX H         : "HL stages 3006H" 
ADD M         : "Add second operand" 
INX H         : "HL stages 3007H" 
MOV M, A      : "Store result at 3007H" 
HLT           : "Exit program" 

Exchanging the Memory Locations

Write a program to exalter the data at 5000M& 6000M memory location.

LDA 5000M   : "Getting the contents at5000M location into accumulator" 
MOV B, A    : "Save the contents into B register" 
LDA 6000M   : "Getting the contents at 6000M location into accumulator" 
STA 5000M   : "Store the contents of accumulator at adgown 5000M" 
MOV A, B    : "Get the saved contents back into A register" 
STA 6000M   : "Store the contents of accumulator at adgown 6000M" 

Arrange Numend up beingrs in an Ascending Order

Write a program to arrange 1st 10 numend up beingrs from memory adgown 3000H in an ascending order.

MVI B, 09         :"Initialize counter"      
START             :"LXI H, 3000H: Initialize memory stageer" 
MVI C, 09H        :"Initialize counter 2" 
BACK: MOV A, M    :"Get the numend up beingr" 
INX H             :"Increment memory stageer" 
CMP M             :"Compare numend up beingr with next numend up beingr" 
JC SKIP           :"If less, don’t interalter" 
JZ SKIP           :"If equal, don’t interalter" 
MOV D, M 
MOV M, A 
DCX H 
MOV M, D 
INX H             :"Interalter two numend up beingrs" 
SKIP:DCR C        :"Decrement counter 2" 
JNZ BACK          :"If not zero, repeat" 
DCR B             :"Decrement counter 1" 
JNZ START 
HLT               :"Terminate program execution" 

Microprocessor – 8086 Overwatch

8086 Microprocessor is an enhanced version of 8085Microprocessor tmind put on was styleed simply simply by Intel in 1976. It is a 16-bit Microprocessor having 20 adgown seriess and16 data seriess tmind put on provides up to 1MB storage. It consists of powerful instruction set, which provides operations like multiplication and division easily.

It supports two modes of operation, i.e. Maximum mode and Minimum mode. Maximum mode is suitable for system having multiple processors and Minimum mode is suitable for system having a performle processor.

Features of 8086

The many prominent features of a 8086 microprocessor are as follows −

  • It has an instruction queue, which is capable of storing six instruction simply simply bytes from the memory resulting in quicker procesperform.

  • It was the 1st 16-bit processor having 16-bit ALU, 16-bit registers, internal data bus, and 16-bit external data bus resulting in quicker procesperform.

  • It is available in 3 versions based on the frequency of operation −

    • 8086 → 5MHz

    • 8086-2 → 8MHz

    • (c)8086-1 → 10 MHz

  • It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage, which improves performance.

  • Fetch stage can prefetch up to 6 simply simply bytes of instructions and stores all of all of them in the queue.

  • Execute stage executes these instructions.

  • It has 256 vectored-coloureddish interrupts.

  • It consists of 29,000 transistors.

Comparison end up beingtween 8085 & 8086 Microprocessor

  • Size − 8085 is 8-bit microprocessor, whereas 8086 is 16-bit microprocessor.

  • Adgown Bus − 8085 has 16-bit adgown bus while 8086 has 20-bit adgown bus.

  • Memory − 8085 can access up to 64Kb, whereas 8086 can access up to 1 Mb of memory.

  • Instruction − 8085 doesn’t have an instruction queue, whereas 8086 has an instruction queue.

  • Pipelining − 8085 doesn’t support a pipeseriesd architecture while 8086 supports a pipeseriesd architecture.

  • I/O − 8085 can adgown 2^8 = 256 I/O's, whereas 8086 can access 2^16 = 65,536 I/O's.

  • Cost − The cost of 8085 is low whereas tmind put on of 8086 is high.

Architecture of 8086

The folloearng diagram depicts the architecture of a 8086 Microprocessor −

Architecture of 8086

Microprocessor – 8086 Functional Unit is

8086 Microprocessor is divided into two functional device’s, i.e., EU (Execution Unit) and BIU (Bus Interface Unit).

EU (Execution Unit)

Execution device gives instructions to BIU stating from where to fetch the data and then decode and execute those instructions. It’s function is to manage operations on data uperform the instruction decoder & ALU. EU has no immediate connection with system buses as shown in the above figure, it performs operations over data through BIU.

Let us now discuss the functional parts of 8086 microprocessors.

ALU

It handles all arithmetic and logical operations, like +, −, ×, /, OR, AND, NOT operations.

Flag Register

It is a 16-bit register tmind put on end up beinghaves like a flip-flop, i.e. it alters it is status according to the result stored-coloureddish in the accumulator. It has 9 flags and they are divided into 2 groups − Conditional Flags and Control Flags.

Conditional Flags

It represents the result of the final arithmetic or logical instruction executed. Folloearng is the list of conditional flags −

  • Carry flag − This flag indicates an overflow condition for arithmetic operations.

  • Auxiliary flag − When an operation is performed at ALU, it results in a carry/barseries from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), then this particular particular flag is set, i.e. carry given simply simply by D3 bit to D4 is AF flag. The processor uses this particular particular flag to perform binary to BCD conversion.

  • Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-bit is of the result contains behaveually numend up beingr of 1’s, then the Parity Flag is set. For odd numend up beingr of 1’s, the Parity Flag is reset.

  • Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it is set to 0.

  • Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is negative, then the sign flag is set to 1 else set to 0.

  • Overflow flag − This flag represents the result when the system capacity is exceeded.

Control Flags

Control flags manages the operations of the execution device. Folloearng is the list of manage flags −

  • Trap flag − It is used for performle step manage and permit is the user to execute one instruction at a time for debugging. If it is set, then the program can end up being operate in a performle step mode.

  • Interrupt flag − It is an interrupt enable/disable flag, i.e. used to permit/prohibit the interruption of a program. It is set to 1 for interrupt enabdirected condition and set to 0 for interrupt disabdirected condition.

  • Direction flag − It is used in string operation. As the name suggests when it is set then string simply simply bytes are accessed from the higher memory adgown to the lower memory adgown and vice-a-versa.

General purpose register

There are 8 general purpose registers, i.e., AH, AL, BH, BL, CH, CL, DH, and DL. These registers can end up being used individually to store 8-bit data and can end up being used in pairs to store 16bit data. The valid register pairs are AH and AL, BH and BL, CH and CL, and DH and DL. It is referred-coloureddish to the AX, BX, CX, and DX respectively.

  • AX register − It is furthermore belowstandn as accumulator register. It is used to store operands for arithmetic operations.

  • BX register − It is used as a base register. It is used to store the starting base adgown of the memory area wislim the data segment.

  • CX register − It is referred-coloureddish to as counter. It is used in loop instruction to store the loop counter.

  • DX register − This register is used to hold I/O port adgown for I/O instruction.

Stack stageer register

It is a 16-bit register, which holds the adgown from the start of the segment to the memory location, where a word was many latestly stored-coloureddish on the stack.

BIU (Bus Interface Unit)

BIU gets care of all data and adgownes transfers on the buses for the EU like sending adgownes, fetching instructions from the memory, reading data from the ports and the memory as well as writing data to the ports and the memory. EU has no immediateion connection with System Buses so this particular particular is achievable with the BIU. EU and BIU are connected with the Internal Bus.

It has the folloearng functional parts −

  • Instruction queue − BIU contains the instruction queue. BIU gets upto 6 simply simply bytes of next instructions and stores all of all of them in the instruction queue. When EU executes instructions and is ready for it is next instruction, then it simply reads the instruction from this particular particular instruction queue resulting in incrreare locatedved execution speed.

  • Fetching the next instruction while the current instruction executes is caldirected pipelining.

  • Segment register − BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the adgownes of instructions and data in memory, which are used simply simply by the processor to access memory locations. It furthermore contains 1 stageer register IP, which holds the adgown of the next instruction to executed simply simply by the EU.

    • CS − It stands for Code Segment. It is used for addresperform a memory location in the code segment of the memory, where the executable program is stored-coloureddish.

    • DS − It stands for Data Segment. It consists of data used simply simply by the program andis accessed in the data segment simply simply by an awayset adgown or the content of other register tmind put on holds the awayset adgown.

    • SS − It stands for Stack Segment. It handles memory to store data and adgownes during execution.

    • ES − It stands for Extra Segment. ES is additional data segment, which is used simply simply by the string to hold the extra destination data.

  • Instruction stageer − It is a 16-bit register used to hold the adgown of the next instruction to end up being executed.

Microprocessor – 8086 Pin Configuration

8086 was the 1st 16-bit microprocessor available in 40-pin DIP (Dual Inseries Package) chip. Let us now discuss in detail the pin configuration of a 8086 Microprocessor.

8086 Pin Diagram

Here is the pin diagram of 8086 microprocessor −

8086 Pin Diagram

Let us now discuss the signals in detail −

Power supply and frequency signals

It uses 5V DC supply at VCC pin 40, and uses ground at VSS pin 1 and 20 for it is operation.

Clock signal

Clock signal is provided through Pin-19. It provides timing to the processor for operations. It’s frequency is various for various versions, i.e. 5MHz, 8MHz and 10MHz.

Adgown/data bus

AD0-AD15. These are 16 adgown/data bus. AD0-AD7 carries low order simply simply byte data and AD8AD15 carries higher order simply simply byte data. During the 1st clock cycle, it carries 16-bit adgown and after tmind put on it carries 16-bit data.

Adgown/status bus

A16-A19/S3-S6. These are the 4 adgown/status buses. During the 1st clock cycle, it carries 4-bit adgown and later it carries status signals.

S7/BHE

BHE stands for Bus High Enable. It is available at pin 34 and used to indicate the transfer of data uperform data bus D8-D15. This signal is low during the 1st clock cycle, generally appropriate now thereafter it is behaveive.

Read($overseries{RD}$)

It is available at pin 32 and is used to read signal for Read operation.

Ready

It is available at pin 32. It is an acbelowstandladvantagement signal from I/O devices tmind put on data is transferred-coloureddish. It is an behaveive high signal. When it is high, it indicates tmind put on the device is ready to transfer data. When it is low, it indicates wait around state.

RESET

It is available at pin 21 and is used to restart the execution. It causes the processor to immediately terminate it is present behaveivity. This signal is behaveive high for the 1st 4 clock cycles to RESET the microprocessor.

INTR

It is available at pin 18. It is an interrupt request signal, which is sampdirected during the final clock cycle of every instruction to figure out if the processor conaspectred-coloureddish this particular particular as an interrupt or not.

NMI

It stands for non-maskable interrupt and is available at pin 17. It is an advantage triggered-coloureddish input, which causes an interrupt request to the microprocessor.

$overseries{TEST}$

This signal is like wait around state and is available at pin 23. When this particular particular signal is high, then the processor has to wait around for IDLE state, else the execution continues.

MN/$overseries{MX}$

It stands for Minimum/Maximum and is available at pin 33. It indicates exbehavely wmind put on mode the processor is to operate in; when it is high, it works in the minimum mode and vice-aversa.

INTA

It is an interrupt acbelowstandladvantagement signal and id available at pin 24. When the microprocessor receives this particular particular signal, it acbelowstandladvantages the interrupt.

ALE

It stands for adgown enable latch and is available at pin 25. A positive pulse is generated every time the processor end up beinggins any operation. This signal indicates the availcapacity of a valid adgown on the adgown/data seriess.

DEN

It stands for Data Enable and is available at pin 26. It is used to enable Transreceiver 8286. The transreceiver is a device used to separate data from the adgown/data bus.

DT/R

It stands for Data Transmit/Receive signal and is available at pin 27. It figure outs the immediateion of data flow through the transreceiver. When it is high, data is transmitted out generally appropriate now there and vice-a-versa.

M/IO

This signal is used to distinguish end up beingtween memory and I/O operations. When it is high, it indicates I/O operation and when it is low indicates the memory operation. It is available at pin 28.

WR

It stands for write signal and is available at pin 29. It is used to write the data into the memory or the out generally appropriate now thereput device depending on the status of M/IO signal.

HLDA

It stands for Hold Acbelowstandladvantagement signal and is available at pin 30. This signal acbelowstandladvantages the HOLD signal.

HOLD

This signal indicates to the processor tmind put on external devices are requesting to access the adgown/data buses. It is available at pin 31.

QS1 and QS0

These are queue status signals and are available at pin 24 and 25. These signals provide the status of instruction queue. Their conditions are shown in the folloearng table −

QS0 QS1 Status
0 0 No operation
0 1 First simply simply byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent simply simply byte from the queue

S0, S1, S2

These are the status signals tmind put on provide the status of operation, which is used simply simply by the Bus Controller 8288 to generate memory & I/O manage signals. These are available at pin 26, 27, and 28. Folloearng is the table footweararng their particular own status −

S2 S1 S0 Status
0 0 0 Interrupt acbelowstandladvantagement
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode fetch
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive

LOCK

When this particular particular signal is behaveive, it indicates to the other processors not to ask the CPU to depart the system bus. It is behaveivated uperform the LOCK prefix on any instruction and is available at pin 29.

RQ/GT1 and RQ/GT0

These are the Request/Grant signals used simply simply by the other processors requesting the CPU to relreare locatedve the system bus. When the signal is received simply simply by CPU, then it sends acbelowstanddirectedgment. RQ/GT0 has a higher priority than RQ/GT1.

Microprocessor – 8086 Instruction Sets

The 8086 microprocessor supports 8 kinds of instructions −

  • Data Transfer Instructions
  • Arithmetic Instructions
  • Bit Manipulation Instructions
  • String Instructions
  • Program Execution Transfer Instructions (Branch & Loop Instructions)
  • Processor Control Instructions
  • Iteration Control Instructions
  • Interrupt Instructions

Let us now discuss these instruction sets in detail.

Data Transfer Instructions

These instructions are used to transfer the data from the source operand to the destination operand. Folloearng are the list of instructions below this particular particular group −

Instruction to transfer a word

  • MOV − Used to duplicate the simply simply byte or word from the provided source to the provided destination.

  • PPUSH − Used to put a word at the top of the stack.

  • POP − Used to get a word from the top of the stack to the provided location.

  • PUSHA − Used to put all the registers into the stack.

  • POPA − Used to get words from the stack to all registers.

  • XCHG − Used to exalter the data from two locations.

  • XLAT − Used to translate a simply simply byte in AL uperform a table in the memory.

Instructions for input and out generally appropriate now thereput port transfer

  • IN − Used to read a simply simply byte or word from the provided port to the accumulator.

  • OUT − Used to send out generally appropriate now there a simply simply byte or word from the accumulator to the provided port.

Instructions to transfer the adgown

  • LEA − Used to load the adgown of operand into the provided register.

  • LDS − Used to load DS register and other provided register from the memory

  • LES − Used to load ES register and other provided register from the memory.

Instructions to transfer flag registers

  • LAHF − Used to load AH with the low simply simply byte of the flag register.

  • SAHF − Used to store AH register to low simply simply byte of the flag register.

  • PUSHF − Used to duplicate the flag register at the top of the stack.

  • POPF − Used to duplicate a word at the top of the stack to the flag register.

Arithmetic Instructions

These instructions are used to perform arithmetic operations like addition, subtrbehaveion, multiplication, division, etc.

Folloearng is the list of instructions below this particular particular group −

Instructions to perform addition

  • ADD − Used to add the provided simply simply byte to simply simply byte/word to word.

  • ADC − Used to add with carry.

  • INC − Used to increment the provided simply simply byte/word simply simply by 1.

  • AAA − Used to adsimply ASCII after addition.

  • DAA − Used to adsimply the decimal after the addition/subtrbehaveion operation.

Instructions to perform subtrbehaveion

  • SUB − Used to subtrbehave the simply simply byte from simply simply byte/word from word.

  • SBB − Used to perform subtrbehaveion with borseries.

  • DEC − Used to decrement the provided simply simply byte/word simply simply by 1.

  • NPG − Used to negate every bit of the provided simply simply byte/word and add 1/2’s complement.

  • CMP − Used to compare 2 provided simply simply byte/word.

  • AAS − Used to adsimply ASCII codes after subtrbehaveion.

  • DAS − Used to adsimply decimal after subtrbehaveion.

Instruction to perform multiplication

  • MUL − Used to multiply unsigned simply simply byte simply simply by simply simply byte/word simply simply by word.

  • IMUL − Used to multiply signed simply simply byte simply simply by simply simply byte/word simply simply by word.

  • AAM − Used to adsimply ASCII codes after multiplication.

Instructions to perform division

  • DIV − Used to divide the unsigned word simply simply by simply simply byte or unsigned double word simply simply by word.

  • IDIV − Used to divide the signed word simply simply by simply simply byte or signed double word simply simply by word.

  • AAD − Used to adsimply ASCII codes after division.

  • CBW − Used to fill the upper simply simply byte of the word with the copies of sign bit of the lower simply simply byte.

  • CWD − Used to fill the upper word of the double word with the sign bit of the lower word.

Bit Manipulation Instructions

These instructions are used to perform operations where data lttle bit is are involved, i.e. operations like logical, shift, etc.

Folloearng is the list of instructions below this particular particular group −

Instructions to perform logical operation

  • NOT − Used to invert every bit of a simply simply byte or word.

  • AND − Used for adding every bit in a simply simply byte/word with the corresponding bit in one more simply simply byte/word.

  • OR − Used to multiply every bit in a simply simply byte/word with the corresponding bit in one more simply simply byte/word.

  • XOR − Used to perform Exclusive-OR operation over every bit in a simply simply byte/word with the corresponding bit in one more simply simply byte/word.

  • TEST − Used to add operands to update flags, without generally appropriate now there affecting operands.

Instructions to perform shift operations

  • SHL/SAL − Used to shift bit is of a simply simply byte/word towards left and put zero(S) in LSBs.

  • SHR − Used to shift bit is of a simply simply byte/word towards the appropriate and put zero(S) in MSBs.

  • SAR − Used to shift bit is of a simply simply byte/word towards the appropriate and duplicate the old MSB into the brand new MSB.

Instructions to perform rotate operations

  • ROL − Used to rotate bit is of simply simply byte/word towards the left, i.e. MSB to LSB and to Carry Flag [CF].

  • ROR − Used to rotate bit is of simply simply byte/word towards the appropriate, i.e. LSB to MSB and to Carry Flag [CF].

  • RCR − Used to rotate bit is of simply simply byte/word towards the appropriate, i.e. LSB to CF and CF to MSB.

  • RCL − Used to rotate bit is of simply simply byte/word towards the left, i.e. MSB to CF and CF to LSB.

String Instructions

String is a group of simply simply bytes/words and their particular own memory is always allocated in a sequential order.

Folloearng is the list of instructions below this particular particular group −

  • REP − Used to repeat the given instruction till CX ≠ 0.

  • REPE/REPZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

  • REPNE/REPNZ − Used to repeat the given instruction until CX = 0 or zero flag ZF = 1.

  • MOVS/MOVSB/MOVSW − Used to move the simply simply byte/word from one string to one more.

  • COMS/COMPSB/COMPSW − Used to compare two string simply simply bytes/words.

  • INS/INSB/INSW − Used as an input string/simply simply byte/word from the I/O port to the provided memory location.

  • OUTS/OUTSB/OUTSW − Used as an out generally appropriate now thereput string/simply simply byte/word from the provided memory location to the I/O port.

  • SCAS/SCASB/SCASW − Used to scan a string and compare it is simply simply byte with a simply simply byte in AL or string word with a word in AX.

  • LODS/LODSB/LODSW − Used to store the string simply simply byte into AL or string word into AX.

Program Execution Transfer Instructions (Branch and Loop Instructions)

These instructions are used to transfer/branch the instructions during an execution. It includes the folloearng instructions −

Instructions to transfer the instruction during an execution without generally appropriate now there any condition −

  • CALL − Used to call a procedure and save their particular own return adgown to the stack.

  • RET − Used to return from the procedure to the main program.

  • JMP − Used to jump to the provided adgown to proceed to the next instruction.

Instructions to transfer the instruction during an execution with a few conditions −

  • JA/JNBE − Used to jump if above/not end up beinglow/equal instruction satisfies.

  • JAE/JNB − Used to jump if above/not end up beinglow instruction satisfies.

  • JBE/JNA − Used to jump if end up beinglow/equal/ not above instruction satisfies.

  • JC − Used to jump if carry flag CF = 1

  • JE/JZ − Used to jump if equal/zero flag ZF = 1

  • JG/JNLE − Used to jump if greater/not less than/equal instruction satisfies.

  • JGE/JNL − Used to jump if greater than/equal/not less than instruction satisfies.

  • JL/JNGE − Used to jump if less than/not greater than/equal instruction satisfies.

  • JLE/JNG − Used to jump if less than/equal/if not greater than instruction satisfies.

  • JNC − Used to jump if no carry flag (CF = 0)

  • JNE/JNZ − Used to jump if not equal/zero flag ZF = 0

  • JNO − Used to jump if no overflow flag OF = 0

  • JNP/JPO − Used to jump if not parity/parity odd PF = 0

  • JNS − Used to jump if not sign SF = 0

  • JO − Used to jump if overflow flag OF = 1

  • JP/JPE − Used to jump if parity/parity behaveually PF = 1

  • JS − Used to jump if sign flag SF = 1

Processor Control Instructions

These instructions are used to manage the processor behaveion simply simply by setting/resetting the flag values.

Folloearng are the instructions below this particular particular group −

  • STC − Used to set carry flag CF to 1

  • CLC − Used to clear/reset carry flag CF to 0

  • CMC − Used to put complement at the state of carry flag CF.

  • STD − Used to set the immediateion flag DF to 1

  • CLD − Used to clear/reset the immediateion flag DF to 0

  • STI − Used to set the interrupt enable flag to 1, i.e., enable INTR input.

  • CLI − Used to clear the interrupt enable flag to 0, i.e., disable INTR input.

Iteration Control Instructions

These instructions are used to execute the given instructions for numend up beingr of times. Folloearng is the list of instructions below this particular particular group −

  • LOOP − Used to loop a group of instructions until the condition satisfies, i.e., CX = 0

  • LOOPE/LOOPZ − Used to loop a group of instructions till it satisfies ZF = 1 & CX = 0

  • LOOPNE/LOOPNZ − Used to loop a group of instructions till it satisfies ZF = 0 & CX = 0

  • JCXZ − Used to jump to the provided adgown if CX = 0

Interrupt Instructions

These instructions are used to call the interrupt during program execution.

  • INT − Used to interrupt the program during execution and calling service specified.

  • INTO − Used to interrupt the program during execution if OF = 1

  • IRET − Used to return from interrupt service to the main program

Microprocessor – 8086 Interrupts

Interrupt is the method of creating a temporary halt during program execution and permit is peripheral devices to access the microprocessor. The microprocessor responds to tmind put on interrupt with an ISR (Interrupt Service Rout generally appropriate now thereine), which is a short program to instruct the microprocessor on how to handle the interrupt.

The folloearng image shows the kinds of interrupts we have in a 8086 microprocessor −

Interrupts

Hardware Interrupts

Hardware interrupt is caused simply simply by any peripheral device simply simply by sending a signal through a specified pin to the microprocessor.

The 8086 has two hardware interrupt pins, i.e. NMI and INTR. NMI is a non-maskable interrupt and INTR is a maskable interrupt having lower priority. One more interrupt pin associated is INTA caldirected interrupt acbelowstandladvantage.

NMI

It is a performle non-maskable interrupt pin (NMI) having higher priority than the maskable interrupt request pin (INTR)and it is of kind 2 interrupt.

When this particular particular interrupt is behaveivated, these behaveions get place −

  • Comppermites the current instruction tmind put on is within progress.

  • Pushes the Flag register values on to the stack.

  • Pushes the CS (code segment) value and IP (instruction stageer) value of the return adgown on to the stack.

  • IP is loaded from the contents of the word location 00008H.

  • CS is loaded from the contents of the next word location 0000AH.

  • Interrupt flag and trap flag are reset to 0.

INTR

The INTR is a maskable interrupt end up beingcause the microprocessor will end up being interrupted only if interrupts are enabdirected uperform set interrupt flag instruction. It need to not end up being enabdirected uperform clear interrupt Flag instruction.

The INTR interrupt is behaveivated simply simply by an I/O port. If the interrupt is enabdirected and NMI is disabdirected, then the microprocessor 1st comppermites the current execution and sends ‘0’ on INTA pin twice. The 1st ‘0’ means INTA informs the external device to get ready and during the second ‘0’ the microprocessor receives the 8 bit, say X, from the programmable interrupt manageler.

These behaveions are getn simply simply by the microprocessor −

  • First comppermites the current instruction.

  • Activates INTA out generally appropriate now thereput and receives the interrupt kind, say X.

  • Flag register value, CS value of the return adgown and IP value of the return adgown are pushed on to the stack.

  • IP value is loaded from the contents of word location X × 4

  • CS is loaded from the contents of the next word location.

  • Interrupt flag and trap flag is reset to 0

Software Interrupts

Some instructions are inserted at the desired-coloureddish position into the program to produce interrupts. These interrupt instructions can end up being used to check the worcalifornia ruler of various interrupt handlers. It includes −

INT- Interrupt instruction with kind numend up beingr

It is 2-simply simply byte instruction. First simply simply byte provides the op-code and the second simply simply byte provides the interrupt kind numend up beingr. There are 256 interrupt kinds below this particular particular group.

It’s execution includes the folloearng steps −

  • Flag register value is pushed on to the stack.

  • CS value of the return adgown and IP value of the return adgown are pushed on to the stack.

  • IP is loaded from the contents of the word location ‘kind numend up beingr’ × 4

  • CS is loaded from the contents of the next word location.

  • Interrupt Flag and Trap Flag are reset to 0

The starting adgown for kind0 interrupt is 000000H, for kind1 interrupt is 00004H similarly for kind2 is 00008H and ……so on. The 1st five stageers are dedicated interrupt stageers. i.e. −

  • TYPE 0 interrupt represents division simply simply by zero situation.

  • TYPE 1 interrupt represents performle-step execution during the debugging of a program.

  • TYPE 2 interrupt represents non-maskable NMI interrupt.

  • TYPE 3 interrupt represents break-stage interrupt.

  • TYPE 4 interrupt represents overflow interrupt.

The interrupts from Type 5 to Type 31 are reserved for other advanced microprocessors, and interrupts from 32 to Type 255 are available for hardware and delicateware interrupts.

INT 3-Break Point Interrupt Instruction

It is a 1-simply simply byte instruction having op-code is CCH. These instructions are inserted into the program so tmind put on when the processor reveryes generally appropriate now there, then it quit’s the normal execution of program and follows the break-stage procedure.

It’s execution includes the folloearng steps −

  • Flag register value is pushed on to the stack.

  • CS value of the return adgown and IP value of the return adgown are pushed on to the stack.

  • IP is loaded from the contents of the word location 3×4 = 0000CH

  • CS is loaded from the contents of the next word location.

  • Interrupt Flag and Trap Flag are reset to 0

INTO – Interrupt on overflow instruction

It is a 1-simply simply byte instruction and their particular own mnemonic INTO. The op-code for this particular particular instruction is CEH. As the name suggests it is a conditional interrupt instruction, i.e. it is behaveive only when the overflow flag is set to 1 and branches to the interrupt handler in in whose interrupt kind numend up beingr is 4. If the overflow flag is reset then, the execution continues to the next instruction.

It’s execution includes the folloearng steps −

  • Flag register values are pushed on to the stack.

  • CS value of the return adgown and IP value of the return adgown are pushed on to the stack.

  • IP is loaded from the contents of word location 4×4 = 00010H

  • CS is loaded from the contents of the next word location.

  • Interrupt flag and Trap flag are reset to 0

Microprocessor – 8086 Addresperform Modes

The various ways in which a source operand is denoted in an instruction is belowstandn as addresperform modes. There are 8 various addresperform modes in 8086 programming −

Immediate addresperform mode

The addresperform mode in which the data operand is a part of the instruction it iself is belowstandn as immediate addresperform mode.

Example

MOV CX, 4929 H, ADD AX, 2387 H,  MOV AL, FFH 

Register addresperform mode

It means tmind put on the register is the source of an operand for an instruction.

Example

MOV CX, AX   ; copies the contents of the 16-bit AX register into  
             ; the 16-bit CX register),  
ADD BX, AX 

Direct addresperform mode

The addresperform mode in which the effective adgown of the memory location is produced immediately in the instruction.

Example

MOV AX, [1592H], MOV AL, [0300H]

Register inimmediate addresperform mode

This addresperform mode permit is data to end up being adgowned at any memory location through an awayset adgown held in any of the folloearng registers: BP, BX, DI & SI.

Example

MOV AX, [BX]  ; Suppose the register BX contains 4895H, then the contents  
              ; 4895H are moved to AX 
ADD CX, {BX} 

Based addresperform mode

In this particular particular addresperform mode, the awayset adgown of the operand is given simply simply by the sum of contents of the BX/BP registers and 8-bit/16-bit displacement.

Example

MOV DX, [BX+04], ADD CL, [BX+08]

Indexed addresperform mode

In this particular particular addresperform mode, the operands awayset adgown is found simply simply by adding the contents of SI or DI register and 8-bit/16-bit displacements.

Example

MOV BX, [SI+16], ADD AL, [DI+16] 

Based-index addresperform mode

In this particular particular addresperform mode, the awayset adgown of the operand is computed simply simply by summing the base register to the contents of an Index register.

Example

ADD CX, [AX+SI], MOV AX, [AX+DI] 

Based indexed with displacement mode

In this particular particular addresperform mode, the operands awayset is computed simply simply by adding the base register contents. An Index registers contents and 8 or 16-bit displacement.

Example

MOV AX, [BX+DI+08], ADD CX, [BX+SI+16] 

Multiprocessor Configuration Overwatch

Multiprocessor means a multiple set of processors tmind put on executes instructions simultaneously. There are 3 fundamental multiprocessor configurations.

  • Coprocessor configuration
  • Closely coupdirected configuration
  • Loosely coupdirected configuration

Coprocessor Configuration

A Coprocessor is a specially styleed circuit on microprocessor chip which can perform the exbehave exact same task very quickly, which the microprocessor performs. It red-coloureddishuces the work load of the main processor. The coprocessor shares the exbehave exact same memory, IO system, bus, manage logic and clock generator. The coprocessor handles specialised tasks like maall of all of thematical calculations, graphical display on screen, etc.

The 8086 and 8088 can perform many of the operations but their particular own instruction set is not able to perform complex maall of all of thematical operations, so in these cases the microprocessor requires the math coprocessor like Intel 8087 math coprocessor, which can easily perform these operations very quickly.

Block Diagram of Coprocessor Configuration

Coprocessor Configuration

How is the coprocessor and the processor connected?

  • The coprocessor and the processor is connected via TEST, RQ-/GT- and QS0 & QS1 signals.

  • The TEST signal is connected to BUSY pin of coprocessor and the remaining 3 pins are connected to the coprocessor’s 3 pins of the exbehave exact same name.

  • TEST signal gets care of the coprocessor’s behaveivity, i.e. the coprocessor is occupied or idle.

  • The RT-/GT-is used for bus arbitration.

  • The coprocessor uses QS0 & QS1 to track the status of the queue of the host processor.

Closely Coupdirected Configuration

Closely coupdirected configuration is similar to the coprocessor configuration, i.e. both share the exbehave exact same memory, I/O system bus, manage logic, and manage generator with the host processor. However, the coprocessor and the host processor fetches and executes their particular own own instructions. The system bus is managedirected simply simply by the coprocessor and the host processor independently.

Block Diagram of Closely Coupdirected Configuration

Closely Coupdirected Configuration

How is the processor and the independent processor connected?

  • Communication end up beingtween the host and the independent processor is done through memory space.

  • None of the instructions are used for communication, like WAIT, ESC, etc.

  • The host processor manages the memory and wakes up the independent processor simply simply by sending commands to one of it is ports.

  • Then the independent processor accesses the memory to execute the task.

  • After comppermition of the task, it sends an acbelowstandladvantagement to the host processor simply simply by uperform the status signal or an interrupt request.

Loosely Coupdirected Configuration

Loosely coupdirected configuration consists of the numend up beingr of modules of the microprocessor based systems, which are connected through a common system bus. Each module consists of their particular own own clock generator, memory, I/O devices and are connected through a local bus.

Block Diagram of Loosely Coupdirected Configuration

Loosely Coupdirected Configuration

Advantages

  • Having more than one processor results in incrreare locatedved efficiency.

  • Each of the processors have their particular own own local bus to access the local memory/I/O devices. This generates it easy to achieve parallel procesperform.

  • The system structure is flexible, i.e. the failure of one module doesn’t affect the whole system failure; faulty module can end up being replaced later.

8087 Numeric Data Processor

8087 numeric data processor is furthermore belowstandn as Math co-processor, Numeric processor extension and Floating stage device. It was the 1st math coprocessor styleed simply simply by Intel to pair with 8086/8088 resulting in easier and quicker calculation.

Once the instructions are identified simply simply by the 8086/8088 processor, then it is allotted to the 8087 co-processor for further execution.

The data kinds supported simply simply by 8087 are −

  • Binary Integers
  • Packed decimal numend up beingrs
  • Real numend up beingrs
  • Temporary real format

The many prominent features of 8087 numeric data processor are as follows −

  • It supports data of kind integer, float, and real kinds ranging from 2-10 simply simply bytes.

  • The procesperform speed is so high tmind put on it can calculate multiplication of two 64-bit is real numend up beingrs in ~27 µs and can furthermore calculate square-belowlying in ~35 µs.

  • It follows IEEE floating stage standards.

8087 Architecture

8087 Architecture is divided into two groups, i.e., Control Unit (CU) and Numeric Extension Unit (NEU).

  • The manage device handles all the communication end up beingtween the processor and the memory such as it receives and decodes instructions, reads and writes memory operands, maintains parallel queue, etc. All the coprocessor instructions are ESC instructions, i.e., they start with ‘F’, the coprocessor only executes the ESC instructions while other instructions are executed simply simply by the microprocessor.

  • The numeric extension device handles all the numeric processor instructions like arithmetic, logical, transcendental, and data transfer instructions. It has 8 register stack, which holds the operands for instructions and their particular own results.

The architecture of 8087 coprocessor is as follows −

Architecture of 8087

8087 Pin Description

Let us 1st get a look at the pin diagram of 8087 −

Pin Diagram 8087

The folloearng list provides the Pin Description of 8087 −

  • AD0 – AD15 − These are the time multiplexed adgown/data seriess, which carry adgownes during the 1st clock cycle and data from the second clock cycle onwards.

  • A19 / S6 – A16/S − These seriess are the time multiplexed adgown/status seriess. It functions in a similar way to the corresponding pins of 8086. The S6, S4 and S3 are permanently high, while the S5 is permanently low.

  • $overseries{BHE}$/S7 − During the 1st clock cycle, the $overseries{BHE}$/S7 is used to enable data on to the higher simply simply byte of the 8086 data bus and after tmind put on works as status series S7.

  • QS1, QS0 − These are queue status input signals which provides the status of instruction queue, their particular own conditions as shown in the folloearng table −

QS0 QS1 Status
0 0 No operation
0 1 First simply simply byte of opcode from the queue
1 0 Empty the queue
1 1 Subsequent simply simply byte from the queue
  • INT − It is an interrupt signal, which alters to high when an unmasked exception has end up beingen received during the execution.

  • BUSY − It is an out generally appropriate now thereput signal, when it is high it indicates a occupied state to the CPU.

  • READY − It is an input signal used to inform the coprocessor whether the bus is ready to receive data or not.

  • RESET − It is an input signal used to reject the internal behaveivities of the coprocessor and prepare it for further execution whenever required-coloureddish simply simply by the CPU.

  • CLK − The CLK input provides the fundamental timings for the processor operation.

  • VCC − It is a power supply signal, which requires +5V supply for the operation of the circuit.

  • S0, S1, S2 − These are the status signals tmind put on provide the status of the operation which is used simply simply by the Bus Controller 8087 to generate memory and I/O manage signals. These signals are behaveive during the fourth clock cycle.

S2 S1 S0 Queue Status
0 X X Unused
1 0 0 Unused
1 0 1 Memory read
1 1 0 Memory write
1 1 1 Passive
  • RQ/GT1 & RQ/GT0 − These are the Request/Grant signals used simply simply by the 8087 processors to gain manage of the bus from the host processor 8086/8088 for operand transfers.

Microprocessor – I/O Interfacing Overwatch

In this particular particular chapter, we will discuss Memory Interfacing and IO Interfacing with 8085.

Interface is the path for communication end up beingtween two components. Interfacing is of two kinds, memory interfacing and I/O interfacing.

Memory Interfacing

When we are executing any instruction, we need the microprocessor to access the memory for reading instruction codes and the data stored-coloureddish in the memory. For this particular particular, both the memory and the microprocessor requires a few signals to read from and write to registers.

The interfacing process includes a few key fbehaveors to complement with the memory requirements and microprocessor signals. The interfacing circuit generally appropriate now therefore need to end up being styleed in such a way tmind put on it complementes the memory signal requirements with the signals of the microprocessor.

IO Interfacing

There are various communication devices like the keypanel, mouse, printer, etc. So, we need to interface the keypanel and other devices with the microprocessor simply simply by uperform latches and buffers. This kind of interfacing is belowstandn as I/O interfacing.

Block Diagram of Memory and I/O Interfacing

Interfacing

8085 Interfacing Pins

Folloearng is the list of 8085 pins used for interfacing with other devices −

  • A15 – A8 (Higher Adgown Bus)
  • AD7 – AD0(Lower Adgown/Data Bus)
  • ALE
  • RD
  • WR
  • READY

Ways of Communication − Microprocessor with the Outaspect World?

There are two ways of communication in which the microprocessor can connect with the out generally appropriate now there’aspect world.

  • Serial Communication Interface
  • Parallel Communication interface

Serial Communication Interface − In this particular particular kind of communication, the interface gets a performle simply simply byte of data from the microprocessor and sends it bit simply simply by bit to the other system serially and vice-a-versa.

Parallel Communication Interface − In this particular particular kind of communication, the interface gets a simply simply byte of data from the microprocessor and sends it bit simply simply by bit to the other systems in simultaneous (or) parallel fashion and vice-a-versa.

8279 – Programmable Keypanel

8279 programmable keypanel/display manageler is styleed simply simply by Intel tmind put on interfaces a keypanel with the CPU. The keypanel 1st scans the keypanel and identifies if any key has end up beingen pressed. It then sends their particular own relative response of the pressed key to the CPU and vice-a-versa.

How Many Ways the Keypanel is Interfaced with the CPU?

The Keypanel can end up being interfaced possibly in the interrupt or the poldirected mode. In the Interrupt mode, the processor is requested service only if any key is pressed, otherwise the CPU will continue with it is main task.

In the Poldirected mode, the CPU periodically reads an internal flag of 8279 to check whether any key is pressed or not with key pressure.

How Does 8279 Keypanel Work?

The keypanel consists of maximum 64 keys, which are interfaced with the CPU simply simply by uperform the key-codes. These key-codes are de-bounced and stored-coloureddish in an 8-simply simply byte FIFORAM, which can end up being accessed simply simply by the CPU. If more than 8 charbehaveers are entered-coloureddish in the FIFO, then it means more than eight keys are pressed at a time. This is when the overoperate status is set.

If a FIFO contains a valid key entest out, then the CPU is withinterrupted in an interrupt mode else the CPU checks the status in polling to read the entest out. Once the CPU reads a key entest out, then FIFO is updated, and the key entest out is pushed out generally appropriate now there of the FIFO to generate space for brand new entries.

Architecture and Description

8279 Architecture

I/O Control and Data Buffer

This device manages the flow of data through the microprocessor. It is enabdirected only when D is low. It’s data buffer interfaces the external bus of the system with the internal bus of the microprocessor. The pins A0, RD, and WR are used for command, status or data read/write operations.

Control and Timing Register and Timing Control

This device contains registers to store the keypanel, display modes, and other operations as programmed simply simply by the CPU. The timing and manage device handles the timings for the operation of the circuit.

Scan Counter

It has two modes i.e. Encoded mode and Decoded mode. In the encoded mode, the counter provides the binary count tmind put on is to end up being externally decoded to provide the scan seriess for the keypanel and display.

In the decoded scan mode, the counter internally decodes the minimumern significan not 2 bit is and provides a decoded 1 out generally appropriate now there of 4 scan on SL0-SL3.

Return Buffers, Keypanel Debounce, and Control

This device 1st scans the key closure series-wise, if found then the keypanel debounce device debounces the key entest out. In case, the exbehave exact same key is detected, then the code of tmind put on key is immediately transferred-coloureddish to the sensor RAM along with SHIFT & CONTROL key status.

FIFO/Sensor RAM and Status Logic

This device behaves as 8-simply simply byte 1st-in-1st-out generally appropriate now there (FIFO) RAM where the key code of every pressed key is entered-coloureddish into the RAM as per their particular own sequence. The status logic generates an interrupt request after every FIFO read operation till the FIFO gets empty.

In the scanned sensor matrix mode, this particular particular device behaves as sensor RAM where it is every series is loaded with the status of their particular own corresponding series of sensors into the matrix. When the sensor alters it is state, the IRQ series alters to high and interrupts the CPU.

Display Adgown Registers and Display RAM

This device consists of display adgown registers which holds the adgownes of the word currently read/produced simply simply by the CPU to/from the display RAM.

8279 − Pin Description

The folloearng figure shows the pin diagram of 8279 −

8279 Pin Diagram

Data Bus Lines, DB0 – DB7

These are 8 biimmediateional data bus seriess used to transfer the data to/from the CPU.

CLK

The clock input is used to generate internal timings required-coloureddish simply simply by the microprocessor.

RESET

As the name suggests this particular particular pin is used to reset the microprocessor.

CS Chip Select

When this particular particular pin is set to low, it permit is read/write operations, else this particular particular pin need to end up being set to high.

A0

This pin indicates the transfer of command/status information. When it is low, it indicates the transfer of data.

RD, WR

This Read/Write pin enables the data buffer to send/receive data over the data bus.

IRQ

This withinterrupt out generally appropriate now thereput series goes high when generally appropriate now there is data in the FIFO sensor RAM. The interrupt series goes low with every FIFO RAM read operation. However, if the FIFO RAM further contains any key-code entest out to end up being read simply simply by the CPU, this particular particular pin again goes high to generate an interrupt to the CPU.

Vss, Vcc

These are the ground and power supply seriess of the microprocessor.

SL0 − SL3

These are the scan seriess used to scan the keypanel matrix and display the digit is. These seriess can end up being programmed as encoded or decoded, uperform the mode manage register.

RL0 − RL7

These are the Return Lines which are connected to one terminal of keys, while the other terminal of the keys is connected to the decoded scan seriess. These seriess are set to 0 when any key is pressed.

SHIFT

The Shift input series status is stored-coloureddish along with every key code in FIFO in the scanned keypanel mode. Till it is drawed low with a key closure, it is drawed up internally to maintain it high

CNTL/STB – CONTROL/STROBED I/P Mode

In the keypanel mode, this particular particular series is used as a manage input and stored-coloureddish in FIFO on a key closure. The series is a stroend up being series tmind put on enters the data into FIFO RAM, in the stroend up beingd input mode. It has an internal draw up. The series is drawed down with a key closure.

BD

It stands for blank display. It is used to blank the display during digit switching.

OUTA0 – OUTA3 and OUTB0 – OUTB3

These are the out generally appropriate now thereput ports for two 16×4 or one 16×8 internal display refresh registers. The data from these seriess is synchronized with the scan seriess to scan the display and the keypanel.

Operational Modes of 8279

There are two modes of operation on 8279 − Input Mode and Output Mode.

Input Mode

This mode deals with the input given simply simply by the keypanel and this particular particular mode is further courseified into 3 modes.

  • Scanned Keypanel Mode − In this particular particular mode, the key matrix can end up being interfaced uperform possibly encoded or decoded scans. In the encoded scan, an 8×8 keypanel or in the decoded scan, a 4×8 keypanel can end up being interfaced. The code of key pressed with SHIFT and CONTROL status is stored-coloureddish into the FIFO RAM.

  • Scanned Sensor Matrix − In this particular particular mode, a sensor array can end up being interfaced with the processor uperform possibly encoder or decoder scans. In the encoder scan, 8×8 sensor matrix or with decoder scan 4×8 sensor matrix can end up being interfaced.

  • Stroend up beingd Input − In this particular particular mode, when the manage series is set to 0, the data on the return seriess is stored-coloureddish in the FIFO simply simply byte simply simply by simply simply byte.

Output Mode

This mode deals with display-related operations. This mode is further courseified into two out generally appropriate now thereput modes.

  • Display Scan − This mode permit is 8/16 charbehaveer multiplexed displays to end up being organised as dual 4-bit/performle 8-bit display device’s.

  • Display Entest out − This mode permit is the data to end up being entered-coloureddish for display possibly from the appropriate aspect/left aspect.

Microprocessor – 8257 DMA Controller

DMA stands for Direct Memory Access. It is styleed simply simply by Intel to transfer data at the fascheck rate. It permit is the device to transfer the data immediately to/from memory without generally appropriate now there any interference of the CPU.

Uperform a DMA manageler, the device requests the CPU to hold it is data, adgown and manage bus, so the device is free to transfer data immediately to/from the memory. The DMA data transfer is withinitiated only after receiving HLDA signal from the CPU.

How DMA Operations are Performed?

Folloearng is the sequence of operations performed simply simply by a DMA −

  • Initially, when any device has to send data end up beingtween the device and the memory, the device has to send DMA request (DRQ) to DMA manageler.

  • The DMA manageler sends Hold request (HRQ) to the CPU and wait arounds for the CPU to assert the HLDA.

  • Then the microprocessor tri-states all the data bus, adgown bus, and manage bus. The CPU departs the manage over bus and acbelowstandladvantages the HOLD request through HLDA signal.

  • Now the CPU is within HOLD state and the DMA manageler has to manage the operations over buses end up beingtween the CPU, memory, and I/O devices.

Features of 8257

Here is a list of a few of the prominent features of 8257 −

  • It has four channels which can end up being used over four I/O devices.

  • Each channel has 16-bit adgown and 14-bit counter.

  • Each channel can transfer data up to 64kb.

  • Each channel can end up being programmed independently.

  • Each channel can perform read transfer, write transfer and verify transfer operations.

  • It generates MARK signal to the peripheral device tmind put on 128 simply simply bytes have end up beingen transferred-coloureddish.

  • It requires a performle phase clock.

  • It’s frequency ranges from 250Hz to 3MHz.

  • It operates in 2 modes, i.e., Master mode and Slave mode.

8257 Architecture

The folloearng image shows the architecture of 8257 −

8257 Architecture

8257 Pin Description

The folloearng image shows the pin diagram of a 8257 DMA manageler −

8257 Pin Diagram

DRQ0−DRQ3

These are the four individual channel DMA request inputs, which are used simply simply by the peripheral devices for uperform DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3 has the lowest priority among all of all of them.

DACKo − DACK3

These are the behaveive-low DMA acbelowstandladvantage seriess, which updates the requesting peripheral about generally appropriate now there the status of their particular own request simply simply by the CPU. These seriess can furthermore behave as stroend up being seriess for the requesting devices.

Do − D7

These are biimmediateional, data seriess which are used to interface the system bus with the internal data bus of DMA manageler. In the Slave mode, it carries command words to 8257 and status word from 8257. In the master mode, these seriess are used to send higher simply simply byte of the generated adgown to the latch. This adgown is further latched uperform ADSTB signal.

IOR

It is an behaveive-low biimmediateional tri-state input series, which is used simply simply by the CPU to read internal registers of 8257 in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a memory write cycle.

IOW

It is an behaveive low bi-immediateion tri-state series, which is used to load the contents of the data bus to the 8-bit mode register or upper/lower simply simply byte of a 16-bit DMA adgown register or terminal count register. In the master mode, it is used to load the data to the peripheral devices during DMA memory read cycle.

CLK

It is a clock frequency signal which is required-coloureddish for the internal operation of 8257.

RESET

This signal is used to RESET the DMA manageler simply simply by disabling all the DMA channels.

Ao – A3

These are the four minimumern significan not adgown seriess. In the slave mode, they behave as an input, which selects one of the registers to end up being read or produced. In the master mode, they are the four minimumern significan not memory adgown out generally appropriate now thereput seriess generated simply simply by 8257.

CS

It is an behaveive-low chip select series. In the Slave mode, it enables the read/write operations to/from 8257. In the master mode, it disables the read/write operations to/from 8257.

A4 – A7

These are the higher nibble of the lower simply simply byte adgown generated simply simply by DMA in the master mode.

READY

It is an behaveive-high asynchronous input signal, which generates DMA ready simply simply by inserting wait around states.

HRQ

This signal is used to receive the hold request signal from the out generally appropriate now thereput device. In the slave mode, it is connected with a DRQ input series 8257. In Master mode, it is connected with HOLD input of the CPU.

HLDA

It is the hold acbelowstandladvantagement signal which indicates the DMA manageler tmind put on the bus has end up beingen granted to the requesting peripheral simply simply by the CPU when it is set to 1.

MEMR

It is the low memory read signal, which is used to read the data from the adgowned memory locations during DMA read cycles.

MEMW

It is the behaveive-low 3 state signal which is used to write the data to the adgowned memory location during DMA write operation.

ADST

This signal is used to convert the higher simply simply byte of the memory adgown generated simply simply by the DMA manageler into the latches.

AEN

This signal is used to disable the adgown bus/data bus.

TC

It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral devices.

MARK

The mark will end up being behaveivated after every 128 cycles or integral multiples of it from the end up beingginning. It indicates the current DMA cycle is the 128th cycle since the previous MARK out generally appropriate now thereput to the selected peripheral device.

Vcc

It is the power signal which is required-coloureddish for the operation of the circuit.

Micromanagelers – Overwatch

A micromanageler is a small and low-cost microcomputer, which is styleed to perform the specific tasks of emend up beingdded systems like displaying micseriesave’s information, receiving remote signals, etc.

The general micromanageler consists of the processor, the memory (RAM, ROM, EPROM), Serial ports, peripherals (timers, counters), etc.

Difference end up beingtween Microprocessor and Micromanageler

The folloearng table highlights the differences end up beingtween a microprocessor and a micromanageler −

Micromanageler Microprocessor
Micromanagelers are used to execute a performle task wislim an application. Microprocessors are used for huge applications.
It’s styleing and hardware cost is low. It’s styleing and hardware cost is high.
Easy to replace. Not so easy to replace.
It is built with CMOS technology, which requires less power to operate. It’s power consumption is high end up beingcause it has to manage the entire system.
It consists of CPU, RAM, ROM, I/O ports. It doesn’t consist of RAM, ROM, I/O ports. It uses it is pins to interface to peripheral devices.

Types of Micromanagelers

Micromanagelers are divided into various categories based on memory, architecture, bit is and instruction sets. Folloearng is the list of their particular own kinds −

Bit

Based on bit configuration, the micromanageler is further divided into 3 categories.

  • 8-bit micromanageler − This kind of micromanageler is used to execute arithmetic and logical operations like addition, subtrbehaveion, multiplication division, etc. For example, Intel 8031 and 8051 are 8 bit is micromanageler.

  • 16-bit micromanageler − This kind of micromanageler is used to perform arithmetic and logical operations where higher accuracy and performance is required-coloureddish. For example, Intel 8096 is a 16-bit micromanageler.

  • 32-bit micromanageler − This kind of micromanageler is generally used in automatically managedirected appliances like automatic operational machines, medical appliances, etc.

Memory

Based on the memory configuration, the micromanageler is further divided into two categories.

  • External memory micromanageler − This kind of micromanageler is styleed in such a way tmind put on they do not have a program memory on the chip. Hence, it is named as external memory micromanageler. For example: Intel 8031 micromanageler.

  • Emend up beingdded memory micromanageler − This kind of micromanageler is styleed in such a way tmind put on the micromanageler has all programs and data memory, counters and timers, interrupts, I/O ports are emend up beingdded on the chip. For example: Intel 8051 micromanageler.

Instruction Set

Based on the instruction set configuration, the micromanageler is further divided into two categories.

  • CISC − CISC stands for complex instruction set computer. It permit is the user to insert a performle instruction as an alternative to many easy instructions.

  • RISC − RISC stands for Reduced Instruction Set Computers. It red-coloureddishuces the operational time simply simply by shortening the clock cycle per instruction.

Applications of Micromanagelers

Micromanagelers are widely used in various various devices such as −

  • Light senperform and manageling devices like LED.

  • Temperature senperform and manageling devices like micseriesave oven, chimneys.

  • Fire detection and securety devices like Fire alprovide.

  • Measuring devices like Volt Meter.

Micromanagelers – 8051 Architecture

8051 micromanageler is styleed simply simply by Intel in 1981. It is an 8-bit micromanageler. It is built with 40 pins DIP (dual inseries package), 4kb of ROM storage and 128 simply simply bytes of RAM storage, 2 16-bit timers. It consists of are four parallel 8-bit ports, which are programmable as well as adgownable as per the requirement. An on-chip crystal oscillator is withintegrated in the micromanageler having crystal frequency of 12 MHz.

Let us now discuss the architecture of 8051 Micromanageler.

In the folloearng diagram, the system bus connects all the support devices to the CPU. The system bus consists of an 8-bit data bus, a 16-bit adgown bus and bus manage signals. All other devices like program memory, ports, data memory, serial interface, interrupt manage, timers, and the CPU are all interfaced collectively through the system bus.

8051 Architecture

Micromanagelers – 8051 Pin Description

The pin diagram of 8051 micromanageler looks as follows −

8051 Pin Diagram

  • Pins 1 to 8 − These pins are belowstandn as Port 1. This port doesn’t serve any other functions. It is withinternally drawed up, bi-immediateional I/O port.

  • Pin 9 − It is a RESET pin, which is used to reset the micromanageler to it is preliminary values.

  • Pins 10 to 17 − These pins are belowstandn as Port 3. This port serves a few functions like interrupts, timer input, manage signals, serial communication signals RxD and TxD, etc.

  • Pins 18 & 19 − These pins are used for interfacing an external crystal to get the system clock.

  • Pin 20 − This pin provides the power supply to the circuit.

  • Pins 21 to 28 − These pins are belowstandn as Port 2. It serves as I/O port. Higher order adgown bus signals are furthermore multiplexed uperform this particular particular port.

  • Pin 29 − This is PSEN pin which stands for Program Store Enable. It is used to read a signal from the external program memory.

  • Pin 30 − This is EA pin which stands for External Access input. It is used to enable/disable the external memory interfacing.

  • Pin 31 − This is ALE pin which stands for Adgown Latch Enable. It is used to demultiplex the adgown-data signal of port.

  • Pins 32 to 39 − These pins are belowstandn as Port 0. It serves as I/O port. Lower order adgown and data bus signals are multiplexed uperform this particular particular port.

  • Pin 40 − This pin is used to provide power supply to the circuit.

Micromanagelers 8051 Input Output Ports

8051 micromanagelers have 4 I/O ports every of 8-bit, which can end up being configured-coloureddish as input or out generally appropriate now thereput. Hence, comppermite 32 input/out generally appropriate now thereput pins permit the micromanageler to end up being connected with the peripheral devices.

  • Pin configuration, i.e. the pin can end up being configured-coloureddish as 1 for input and 0 for out generally appropriate now thereput as per the logic state.

    • Input/Output (I/O) pin − All the circuit is wislim the micromanageler must end up being connected to one of it is pins except P0 port end up beingcause it does not have draw-up resistors built-in.

    • Input pin − Logic 1 is applayd to a lttle bit of the P register. The out generally appropriate now thereput FE transistor is turned away and the other pin remains connected to the power supply voltage over a draw-up resistor of high resistance.

  • Port 0 − The P0 (zero) port is charbehaveerized simply simply by two functions −

    • When the external memory is used then the lower adgown simply simply byte (adgownes A0A7) is applayd on it, else all bit is of this particular particular port are configured-coloureddish as input/out generally appropriate now thereput.

    • When P0 port is configured-coloureddish as an out generally appropriate now thereput then other ports consisting of pins with built-in draw-up resistor connected simply simply by it is end to 5V power supply, the pins of this particular particular port have this particular particular resistor left out generally appropriate now there.

Input Configuration

If any pin of this particular particular port is configured-coloureddish as an input, then it behaves as if it “floats”, i.e. the input has unlimited input resistance and in-figure outd feasible.

Output Configuration

When the pin is configured-coloureddish as an out generally appropriate now thereput, then it behaves as an “open up drain”. By applying logic 0 to a port bit, the appropriate pin will end up being connected to ground (0V), and applying logic 1, the external out generally appropriate now thereput will maintain on “floating”.

In order to apply logic 1 (5V) on this particular particular out generally appropriate now thereput pin, it is necessary to construct an external drawup resistor.

Port 1

P1 is a true I/O port as it doesn’t have any alternative functions as in P0, but this particular particular port can end up being configured-coloureddish as general I/O only. It has a built-in draw-up resistor and is comppermitely compatible with TTL circuit is.

Port 2

P2 is similar to P0 when the external memory is used. Pins of this particular particular port occupy adgownes intended for the external memory chip. This port can end up being used for higher adgown simply simply byte with adgownes A8-A15. When no memory is added then this particular particular port can end up being used as a general input/out generally appropriate now thereput port similar to Port 1.

Port 3

In this particular particular port, functions are similar to other ports except tmind put on the logic 1 must end up being applayd to appropriate bit of the P3 register.

Pins Current Limitations

  • When pins are configured-coloureddish as an out generally appropriate now thereput (i.e. logic 0), then the performle port pins can receive a current of 10mA.

  • When these pins are configured-coloureddish as inputs (i.e. logic 1), then built-in draw-up resistors provide very weak current, but can behaveivate up to 4 TTL inputs of LS series.

  • If all 8 bit is of a port are behaveive, then the comppermite current must end up being limited to 15mA (port P0: 26mA).

  • If all ports (32 bit is) are behaveive, then the comppermite maximum current must end up being limited to 71mA.

Micromanagelers – 8051 Interrupts

Interrupts are the behaveuallyts tmind put on temporarily suspend the main program, move the manage to the external sources and execute their particular own task. It then movees the manage to the main program where it had left away.

8051 has 5 interrupt signals, i.e. INT0, TFO, INTR1, TF1, RI/TI. Each interrupt can end up being enabdirected or disabdirected simply simply by setting bit is of the IE register and the whole interrupt system can end up being disabdirected simply simply by clearing the EA bit of the exbehave exact same register.

IE (Interrupt Enable) Register

This register is responsible for enabling and disabling the interrupt. EA register is set to one for enabling interrupts and set to 0 for disabling the interrupts. It’s bit sequence and their particular own meanings are shown in the folloearng figure.

IE Register

EA IE.7 It disables all interrupts. When EA = 0 no interrupt will end up being acbelowstandladvantaged and EA = 1 enables the interrupt individually.
IE.6 Reserved for future use.
IE.5 Reserved for future use.
ES IE.4 Enables/disables serial port interrupt.
ET1 IE.3 Enables/disables timer1 overflow interrupt.
EX1 IE.2 Enables/disables external interrupt1.
ET0 IE.1 Enables/disables timer0 overflow interrupt.
EX0 IE.0 Enables/disables external interrupt0.

IP (Interrupt Priority) Register

We can alter the priority levels of the interrupts simply simply by changing the corresponding bit in the Interrupt Priority (IP) register as shown in the folloearng figure.

  • A low priority interrupt can only end up being interrupted simply simply by the high priority interrupt, but not interrupted simply simply by one more low priority interrupt.

  • If two interrupts of various priority levels are received simultaneously, the request of higher priority level is served.

  • If the requests of the exbehave exact same priority levels are received simultaneously, then the internal polling sequence figure outs which request is to end up being serviced.

IP Register

IP.6 Reserved for future use.
IP.5 Reserved for future use.
PS IP.4 It degreats the serial port interrupt priority level.
PT1 IP.3 It degreats the timer interrupt of 1 priority.
PX1 IP.2 It degreats the external interrupt priority level.
PT0 IP.1 It degreats the timer0 interrupt priority level.
PX0 IP.0 It degreats the external interrupt of 0 priority level.

TCON Register

TCON register specifies the kind of external interrupt to the micromanageler.

8255A – Programmable Peripheral Interface

The 8255A is a general purpose programmable I/O device styleed to transfer the data from I/O to interrupt I/O below specific conditions as required-coloureddish. It can end up being used with almany any microprocessor.

It consists of 3 8-bit biimmediateional I/O ports (24I/O seriess) which can end up being configured-coloureddish as per the requirement.

Ports of 8255A

8255A has 3 ports, i.e., PORT A, PORT B, and PORT C.

  • Port A contains one 8-bit out generally appropriate now thereput latch/buffer and one 8-bit input buffer.

  • Port B is similar to PORT A.

  • Port C can end up being split into two parts, i.e. PORT C lower (PC0-PC3) and PORT C upper (PC7-PC4) simply simply by the manage word.

These 3 ports are further divided into two groups, i.e. Group A includes PORT A and upper PORT C. Group B includes PORT B and lower PORT C. These two groups can end up being programmed in 3 various modes, i.e. the 1st mode is named as mode 0, the second mode is named as Mode 1 and the third mode is named as Mode 2.

Operating Modes

8255A has 3 various operating modes −

  • Mode 0 − In this particular particular mode, Port A and B is used as two 8-bit ports and Port C as two 4-bit ports. Each port can end up being programmed in possibly input mode or out generally appropriate now thereput mode where out generally appropriate now thereputs are latched and inputs are not latched. Ports do not have interrupt capcapacity.

  • Mode 1 − In this particular particular mode, Port A and B is used as 8-bit I/O ports. They can end up being configured-coloureddish as possibly input or out generally appropriate now thereput ports. Each port uses 3 seriess from port C as handshake signals. Inputs and out generally appropriate now thereputs are latched.

  • Mode 2 − In this particular particular mode, Port A can end up being configured-coloureddish as the biimmediateional port and Port B possibly in Mode 0 or Mode 1. Port A uses five signals from Port C as handshake signals for data transfer. The remaining 3 signals from Port C can end up being used possibly as easy I/O or as handshake for port B.

Features of 8255A

The prominent features of 8255A are as follows −

  • It consists of 3 8-bit IO ports i.e. PA, PB, and PC.

  • Adgown/data bus must end up being externally demux'd.

  • It is TTL compatible.

  • It has improved DC driving capcapacity.

8255 Architecture

The folloearng figure shows the architecture of 8255A −

8255A Architecture

Intel 8255A – Pin Description

Let us 1st get a look at the pin diagram of Intel 8255A −

8255A Pin Diagram

Now permit us discuss the functional description of the pins in 8255A.

Data Bus Buffer

It is a tri-state 8-bit buffer, which is used to interface the microprocessor to the system data bus. Data is transmitted or received simply simply by the buffer as per the instructions simply simply by the CPU. Control words and status information is furthermore transferred-coloureddish uperform this particular particular bus.

Read/Write Control Logic

This block is responsible for manageling the internal/external transfer of data/manage/status word. It accepts the input from the CPU adgown and manage buses, and in turn issues command to both the manage groups.

CS

It stands for Chip Select. A LOW on this particular particular input selects the chip and enables the communication end up beingtween the 8255A and the CPU. It is connected to the decoded adgown, and A0 & A1 are connected to the microprocessor adgown seriess.

Their result depends on the folloearng conditions −

CS A1 A0 Result
0 0 0 PORT A
0 0 1 PORT B
0 1 0 PORT C
0 1 1 Control Register
1 X X No Selection

WR

It stands for write. This manage signal enables the write operation. When this particular particular signal goes low, the microprocessor writes into a selected I/O port or manage register.

RESET

This is an behaveive high signal. It clears the manage register and sets all ports in the input mode.

RD

It stands for Read. This manage signal enables the Read operation. When the signal is low, the microprocessor reads the data from the selected I/O port of the 8255.

A0 and A1

These input signals work with RD, WR, and one of the manage signal. Folloearng is the table footweararng their particular own various signals with their particular own result.

A1 A0 RD WR CS Result
0 0 0 1 0

Input Operation

PORT A → Data Bus

0 1 0 1 0 PORT B → Data Bus
1 0 0 1 0 PORT C → Data Bus
0 0 1 0 0

Output Operation

Data Bus → PORT A

0 1 1 0 0 Data Bus → PORT A
1 0 1 0 0 Data Bus → PORT B
1 1 1 0 0 Data Bus → PORT D

Intel 8253 – Programmable Interval Timer

The Intel 8253 and 8254 are Programmable Interval Timers (PTIs) styleed for microprocessors to perform timing and counting functions uperform 3 16-bit registers. Each counter has 2 input pins, i.e. Clock & Gate, and 1 pin for “OUT” out generally appropriate now thereput. To operate a counter, a 16-bit count is loaded in it is register. On command, it end up beinggins to decrement the count until it reveryes 0, then it generates a pulse tmind put on can end up being used to interrupt the CPU.

Difference end up beingtween 8253 and 8254

The folloearng table variousiates the features of 8253 and 8254 −

8253 8254
It’s operating frequency is 0 – 2.6 MHz It’s operating frequency is 0 – 10 MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not available Read-Back command is available
Reads and writes of the exbehave exact same counter cannot end up being interdepartd. Reads and writes of the exbehave exact same counter can end up being interdepartd.

Features of 8253 / 54

The many prominent features of 8253/54 are as follows −

  • It has 3 independent 16-bit down counters.

  • It can handle inputs from DC to 10 MHz.

  • These 3 counters can end up being programmed for possibly binary or BCD count.

  • It is compatible with almany all microprocessors.

  • 8254 has a powerful command caldirected READ BACK command, which permit is the user to check the count value, the programmed mode, the current mode, and the current status of the counter.

8254 Architecture

The architecture of 8254 looks as follows −

8254 Architecture

8254 Pin Description

Here is the pin diagram of 8254 −

8254 Pin Description

In the above figure, generally appropriate now there are 3 counters, a data bus buffer, Read/Write manage logic, and a manage register. Each counter has two input signals – CLOCK & GATE, and one out generally appropriate now thereput signal – OUT.

Data Bus Buffer

It is a tri-state, bi-immediateional, 8-bit buffer, which is used to interface the 8253/54 to the system data bus. It has 3 fundamental functions −

  • Programming the modes of 8253/54.
  • Loading the count registers.
  • Reading the count values.

Read/Write Logic

It includes 5 signals, i.e. RD, WR, CS, and the adgown seriess A0 & A1. In the peripheral I/O mode, the RD and WR signals are connected to IOR and IOW, respectively. In the memorychartped I/O mode, these are connected to MEMR and MEMW.

Adgown seriess A0 & A1 of the CPU are connected to seriess A0 and A1 of the 8253/54, and CS is tied to a decoded adgown. The manage word register and counters are selected according to the signals on seriess A0 & A1.

A1 A0 Result
0 0 Counter 0
0 1 Counter 1
1 0 Counter 2
1 1 Control Word Register
X X No Selection

Control Word Register

This register is accessed when seriess A0 & A1 are at logic 1. It is used to write a command word, which specifies the counter to end up being used, it is mode, and possibly a read or write operation. Folloearng table shows the result for various manage inputs.

A1 A0 RD WR CS Result
0 0 1 0 0 Write Counter 0
0 1 1 0 0 Write Counter 1
1 0 1 0 0 Write Counter 2
1 1 1 0 0 Write Control Word
0 0 0 1 0 Read Counter 0
0 1 0 1 0 Read Counter 1
1 0 0 1 0 Read Counter 2
1 1 0 1 0 No operation
X X 1 1 0 No operation
X X X X 1 No operation

Counters

Each counter consists of a performle, 16 bit-down counter, which can end up being operated in possibly binary or BCD. It’s input and out generally appropriate now thereput is configured-coloureddish simply simply by the selection of modes stored-coloureddish in the manage word register. The programmer can read the contents of any of the 3 counters without generally appropriate now there disturbing the behaveual count in process.

Intel 8253/54 – Operational Modes

8253/54 can end up being operated in 6 various modes. In this particular particular chapter, we will discuss these operational modes.

Mode 0 ─ Interrupt on Terminal Count

  • It is used to generate an interrupt to the microprocessor after a specific interval.

  • Initially the out generally appropriate now thereput is low after the mode is set. The out generally appropriate now thereput remains LOW after the count value is loaded into the counter.

  • The process of decrementing the counter continues till the terminal count is reveryed, i.e., the count end up beingcome zero and the out generally appropriate now thereput goes HIGH and will remain high until it reloads a brand new count.

  • The GATE signal is high for normal counting. When GATE goes low, counting is terminated and the current count is latched till the GATE goes high again.

Mode 1 – Programmable One Shot

  • It can end up being used as a mono stable multi-vibrator.

  • The gate input is used as a trigger input in this particular particular mode.

  • The out generally appropriate now thereput remains high until the count is loaded and a trigger is applayd.

Mode 2 – Rate Generator

  • The out generally appropriate now thereput is normally high after preliminaryization.

  • Whenever the count end up beingcomes zero, one more low pulse is generated at the out generally appropriate now thereput and the counter will end up being reloaded.

Mode 3 – Square Wave Generator

  • This mode is similar to Mode 2 except the out generally appropriate now thereput remains low for half of the timer period and high for the other half of the period.

Mode 4 − Software Triggered-coloureddish Mode

  • In this particular particular mode, the out generally appropriate now thereput will remain high until the timer has counted to zero, at which stage the out generally appropriate now thereput will pulse low and then go high again.

  • The count is latched when the GATE signal goes LOW.

  • On the terminal count, the out generally appropriate now thereput goes low for one clock cycle then goes HIGH. This low pulse can end up being used as a stroend up being.

Mode 5 – Hardware Triggered-coloureddish Mode

  • This mode generates a stroend up being in response to an externally generated signal.

  • This mode is similar to mode 4 except tmind put on the counting is withinitiated simply simply by a signal at the gate input, which means it is hardware triggered-coloureddish instead of delicateware triggered-coloureddish.

  • After it is preliminaryized, the out generally appropriate now thereput goes high.

  • When the terminal count is reveryed, the out generally appropriate now thereput goes low for one clock cycle.

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