VLSI Design

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VLSI Design – Digital System

Very-huge-dimension integration (VLSI) is the process of creating an integrated circuit (IC) simply by combining thougood fine sands of transistors into a single chip. VLSI end up beinggan in the 1970s when complex semiconductor and communication technologies were end up beinging generateed. The miharvestrocessor is a VLSI device.

Before the introduction of VLSI technology, many kind of ICs had a limited set of functions they could perform. An digital circuit may consist of a CPU, ROM, RAM and other glue logic. VLSI permit is IC styleers add all of these into one chip.

The digitals indusconaspectr has achieved a phenomenal grangeth over the final couple of decades, mainly because of to the rapid advances in huge dimension integration technologies and system style applications. With the advent of very huge dimension integration (VLSI) styles, the numend up beingr of applications of integrated circuit is (ICs) in high-performance computing, manages, telecommunications, image and video processing, and consumer digitals has end up beingen rising at an extremely fast pace.

The current cutting-advantage technologies such as high resolution and low bit-rate video and cellularularular communications provide the end-users a marvelous amount of applications, processing power and slotcapability. This trend is expected to grange rapidly, with very imslotant implications on VLSI style and systems style.

VLSI Design Flow

The VLSI IC circuit is style flow is shown in the figure end up beinglow. The various levels of style are numend up beingred and the blocks show processes in the style flow.

Specifications comes preliminary, they descriend up being abstrworkionly, the functionality, interface, and the architecture of the digital IC circuit to end up being styleed.

VLSI Design Flow

Behavioral description is then generated to analyze the style in terms of functionality, performance, compliance to given standards, and other specifications.

RTL description is done using HDLs. This RTL description is simulated to check functionality. From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic synthesis tools. A gatelevel netlist is a description of the circuit in terms of gates and interinterconnections end up beingtween them, which are made in such a way thead wear they meet the timing, power and area specifications.

Finally, a physical layaway presently correct now there is made, which will end up being verified and then sent to fabrication.

Y Chart

The Gajski-Kuhn Y-chart is a model, which captures the conaspectrations in styleing semiconductor devices.

The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the domains can end up being divided into levels of abstrworkionion, using concentric rings.

At the top level (away presently correct now thereer ring), we conaspectr the architecture of the chip; at the lower levels (internal rings), we successively regood the style into goodr detaiimmediateed implementation −

Creating a structural description from a end up beinghavioral one is achieved through the processes of high-level synthesis or logical synthesis.

Creating a physical description from a structural one is achieved through layaway presently correct now there synthesis.

Y-chart

Design Hierarchy-Structural

The style hierarchy involves the principle of "Divide and Conquer." It is absolutely absolutely noslimg but dividing the task into smaller tasks until it reveryes to it is fundamentalst level. This process is many kind of suitable end up beingcause the final evolution of style has end up beingcome so fundamental thead wear it is manurealityionuring end up beingcomes easier.

We can style the given task into the style flow process's domain (Behavioral, Structural, and Geometrical). To belowstand this particular particular, permit’s consider an example of styleing a 16-bit adder, as shown in the figure end up beinglow.

Design Hierarchy-Structural

Here, the whole chip of 16 bit adder is divided into four modules of 4-bit adders. Further, dividing the 4-bit adder into 1-bit adder or half adder. 1 bit addition is the fundamentalst styleing process and it is internal circuit is furthermore easy to fabricate on the chip. Now, connecting all the final four adders, we can style a 4-bit adder and moving on, we can style a 16-bit adder.

4-bit adder

VLSI Design – FPGA Technology

FPGA – Introduction

The comppermite form of FPGA is “Field Programmable Gate Array”. It contains ten thougood fine sand to more than a million logic gates with programmable interinterinterconnection. Programmable interinterinterconnections are available for users or styleers to perform given functions easily. A typical model FPGA chip is shown in the given figure. There are I/O blocks, which are styleed and numend up beingred according to function. For every module of logic level composition, presently correct now there are CLB’s (Configurable Logic Blocks).

CLB performs the logic operation given to the module. The inter interinterconnection end up beingtween CLB and I/O blocks are made with the help of horizontal raway presently correct now thereing channels, vertical raway presently correct now thereing channels and PSM (Programmable Multiplexers).

The numend up beingr of CLB it contains only figure aways the complexity of FPGA. The functionality of CLB’s and PSM are styleed simply by VHDL or any kind of other hardware descriptive language. After programming, CLB and PSM are placed on chip and connected with every other with raway presently correct now thereing channels.

FPGA – Introduction

Advantages

  • It requires very small time; starting from style process to functional chip.
  • No physical manurealityionuring steps are involved in it.
  • The only didepressingvantage is, it is costly than other styles.

Gate Array Design

The gate array (GA) ranks 2nd after the FPGA, in terms of fast prototyping capcapability. While user programming is imslotant to the style implementation of the FPGA chip, metallic mask style and processing is used for GA. Gate array implementation requires a 2-step manurealityionuring process.

The preliminary phase results in an array of uncommitted transistors on every GA chip. These uncommitted chips can end up being stored for later customization, which is comppermited simply by defining the metallic interconnects end up beingtween the transistors of the array. The patterning of metalliclic interconnects is done at the end of the chip fabrication process, so thead wear the turn-around time can still end up being short, a couple of days to a couple of weeks. The figure given end up beinglow shows the fundamental processing steps for gate array implementation.

Gate Array Design

Typical gate array platforms use dedicated areas calimmediateed channels, for inter-cellularular raway presently correct now thereing end up beingtween ranges or columns of MOS transistors. They simplify the interinterinterconnections. Interinterinterconnection patterns thead wear perform fundamental logic gates are stored in a library, which can then end up being used to customise ranges of uncommitted transistors according to the netlist.

In many kind of of the modern GAs, multiple metallic layers are used for channel raway presently correct now thereing. With the use of multiple interconnected layers, the raway presently correct now thereing can end up being achieved over the workionive cellularular areas; so thead wear the raway presently correct now thereing channels can end up being removed as in Sea-of-Gates (SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and pMOS transistors. The neighbouring transistors can end up being customised using a metallic mask to form fundamental logic gates.

For inter cellularular raway presently correct now thereing, a couple of of the uncommitted transistors must end up being sacrificed. This style style results in more flexibility for interinterinterconnections and usually in a higher density. GA chip utilization realityionor is measured simply by the used chip area divided simply by the comppermite chip area. It is higher than thead wear of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cellularular based style requires generatement of a comppermite custom mask set. The standard cellularular is furthermore belowstandn as the polycellularular. In this particular particular approach, all of the commonly used logic cellularulars are generateed, charworkionerized and stored in a standard cellularular library.

A library may contain a couple of 100 cellularulars including inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate kind can end up being implemented in a few versions to provide adequate driving capcapability for various fan-away presently correct now there’s. The inverter gate can have standard dimension, double dimension, and quadruple dimension so thead wear the chip styleer can select the proper dimension to obtain high circuit speed and layaway presently correct now there density.

Each cellularular is charworkionerized according to a few various charworkionerization categories, such as,

  • Delay time versus load capacitance
  • Circuit simulation model
  • Timing simulation model
  • Fault simulation model
  • Cell data for place-and-raway presently correct now theree
  • Mask data

For automated placement of the cellularulars and raway presently correct now thereing, every cellularular layaway presently correct now there is styleed with a fixed height, so thead wear a numend up beingr of cellularulars can end up being bounded aspect-simply by-aspect to form ranges. The power and ground rails operate parallel to the upper and lower boundaries of the cellularular. So thead wear, neighbouring cellularulars share a common power bus and a common ground bus. The figure shown end up beinglow is a floorplan for standard-cellularular based style.

Standard Cell Based Design

Full Custom Design

In a comppermite-custom style, the entire mask style is made brand new, withaway presently correct now there the use of any kind of library. The generatement cost of this particular particular style style is rising. Thus, the concept of style reuse is end up beingcoming famous to reduce style cycle time and generatement cost.

The hardest comppermite custom style can end up being the style of a memory cellularular, end up being it static or dynamic. For logic chip style, a good negotiation can end up being obtained using a combination of various style styles on the exworkion same chip, i.e. standard cellularulars, data-route cellularulars, and programmable logic arrays (PLAs).

Prworkionically, the styleer does the comppermite custom layaway presently correct now there, i.e. the geomeconaspectr, orientation, and placement of every transistor. The style itemivity is usually very low; typically a couple of tens of transistors per day, per styleer. In digital CMOS VLSI, comppermite-custom style is hardly used because of to the high labor cost. These style styles include the style of high-volume items such as memory chips, high-performance miharvestrocessors and FPGA.

VLSI Design – MOS Transistor

Complementary MOSFET (CMOS) technology is widely used today to form circuit is in a few and varied applications. Today’s computers, CPUs and cellularular phones generate use of CMOS because of to a few key advantages. CMOS provides low power dissipation, relatively high speed, high sound margins in both states, and will operate over a wide range of source and input voltages (provided the source voltage is fixed)

For the processes we will discuss, the kind of transistor available is the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). These transistors are formed as a ‘good fine sandwich’ consisting of a semiconductor layer, usually a slice, or wafer, from a single weepstal of silicon; a layer of silicon dioxide (the oxide) and a layer of metallic.

Structure of a MOSFET

Structure of misfet

As shown in the figure, MOS structure contains three layers −

  • The Metal Gate Electrode

  • The Insulating Oxide Layer (SiO2)

  • P – kind Semiconductor (Substrate)

MOS structure forms a capacitor, with gate and substrate are as 2 plates and oxide layer as the expirelectric material. The bigness of expirelectric material (SiO2) is usually end up beingtween 10 nm and 50 nm. Carrier concentration and distribution wislim the substrate can end up being manipulated simply by external voltage apprestd to gate and substrate terminal. Now, to belowstand the structure of MOS, preliminary conaspectr the fundamental electric properconnects of P – Type semiconductor substrate.

Concentration of carrier in semiconductor material is always folloearng the Mass Action Law. Mass Action Law is given simply by −

$$n.p=n_{i}^{2}$$

Where,

  • n is carrier concentration of electrons

  • p is carrier concentration of holes

  • ni is wislimtrinsic carrier concentration of Silicon

Now assume thead wear substrate is equally doped with acceptor (Boron) concentration NA. So, electron and hole concentration in p–kind substrate is

$$n_{po}=frac{n_{i}^{2}}{N_{A}}$$

$$p_{po}=N_{A}$$

Here, doping concentration NA is (1015 to 1016 cm−3) greater than intrinsic concentration ni. Now, to belowstand the MOS structure, conaspectr the energy level diagram of p–kind silicon substrate.

P-kind Silicon Substrate

As shown in the figure, the band gap end up beingtween conduction band and valance band is 1.1eV. Here, Fermi achievable ΦF is the difference end up beingtween intrinsic Fermi level (Ei) and Fermi level (EFP).

Where Fermi level EF depends on the doping concentration. Fermi achievable ΦF is the difference end up beingtween intrinsic Fermi level (Ei) and Fermi level (EFP).

Mathematically,

$$Phi_{Fp}=frac{E_{F}-E_{i}}{q}$$

The achievable difference end up beingtween conduction band and free space is calimmediateed electron affinity and is denoted simply by qx.

So, energy required for an electron to move from Fermi level to free space is calimmediateed work function (qΦS) and it is given simply by

$$qPhi _{s}=(E_{c}-E_{F})+qx$$

The folloearng figure shows the energy band diagram of components thead wear generate up the MOS.

Energy Level Diagram of Components

As shown in the above figure, insulating SiO2 layer has huge energy band gap of 8eV and work function is 0.95 eV. Metal gate has work function of 4.1eV. Here, the work functions are various so it will generate voltage fall amix the MOS system. The figure given end up beinglow shows the combined energy band diagram of MOS system.

Combined Energy Band Diagram

As shown in this particular particular figure, the fermi achievable level of metallic gate and semiconductor (Si) are at exworkion same achievable. Fermi achievable at surface is calimmediateed surface achievable ΦS and it is smaller than Fermi achievable ΦF in magnitude.

Worcalifornia king of a MOSFET

MOSFET consists of a MOS capacitor with 2 p-n junctions placed shut upd to the channel area and this particular particular area is manageimmediateed simply by gate voltage. To generate both the p-n junction reverse biased, substrate achievable is kept lower than the other three terminals achievable.

If the gate voltage will end up being incrrerestved end up beingyond the threshold voltage (VGS>VTO), inversion layer will end up being established on the surface and n – kind channel will end up being formed end up beingtween the source and drain. This n – kind channel will carry the drain current according to the VDS value.

For various value of VDS, MOSFET can end up being operated in various areas as exnormaled end up beinglow.

Linear Region

At VDS = 0, thermal equilibrium exists in the inverted channel area and drain current ID = 0. Now if small drain voltage, VDS > 0 is apprestd, a drain current proslotional to the VDS will start to flow from source to drain through the channel.

The channel gives a continuous route for the flow of current from source to drain. This mode of operation is calimmediateed collectionar area. The mix sectional watch of an n-channel MOSFET, operating in collectionar area, is shown in the figure given end up beinglow.

Linear Region

At the Edge of Saturation Region

Now if the VDS is wislimcrrerestved, charges in the channel and channel depth decrrerestve at the end of drain. For VDS = VDSAT, the charges in the channel is reduces to zero, which is calimmediateed pinch – away from point. The mix sectional watch of n-channel MOSFET operating at the advantage of saturation area is shown in the figure given end up beinglow.

Edge of Saturation Region

Saturation Region

For VDS>VDSAT, a deppermited surface forms near to drain, and simply by increasing the drain voltage this particular particular deppermited area extends to source.

This mode of operation is calimmediateed Saturation area. The electrons coming from the source to the channel end, enter in the drain – deppermition area and are accelerated towards the drain in high electric field.

Saturation Region

MOSFET Current – Voltage Charworkioneristics

To belowstand the current – voltage charworkioneristic of MOSFET, approximation for the channel is done. Withaway presently correct now there this particular particular approximation, the three dimension analysis of MOS system end up beingcomes complex. The Gradual Channel Approximation (GCA) for current – voltage charworkioneristic will reduce the analysis problem.

Gradual Channel Approximation (GCA)

Conaspectr the mix sectional watch of n channel MOSFET operating in the collectionar mode. Here, source and substrate are connected to the ground. VS = VB = 0. The gate – to – source (VGS) and drain – to – source voltage (VDS) voltage are the external parameters thead wear manage the drain current ID.

Gradual Channel Approximation

The voltage, VGS is set to a voltage greater than the threshold voltage VTO, to generate a channel end up beingtween the source and drain. As shown in the figure, x – immediateion is perpendicular to the surface and y – immediateion is parallel to the surface.

Here, y = 0 at the source end as shown in the figure. The channel voltage, with respect to the source, is represented simply by VC(Y). Assume thead wear the threshold voltage VTO is constant asizey the channel area, end up beingtween y = 0 to y = L. The boundary condition for the channel voltage VC are −

$$V_{c}left ( y = 0 appropriate ) = V_{s} = 0 ,and,V_{c}left ( y = L appropriate ) = V_{DS}$$

We can furthermore assume thead wear

$$V_{GS}geq V_{TO}$$ and

$$V_{GD} = V_{GS}-V_{DS}geq V_{TO}$$

Let Q1(y) end up being the comppermite mobile electron charge in the surface inversion layer. This electron charge can end up being expressed as −

$$Q1(y)=-C_{ox}.[V_{GS}-V_{C(Y)}-V_{TO}]$$

The figure given end up beinglow shows the spatial geomeconaspectr of the surface inversion layer and indicate it is dimensions. The inversion layer taper away from as we move from drain to source. Now, if we conaspectr the small area dy of channel dimension L then incremental resistance dR provideed simply by this particular particular area can end up being expressed as −

$$dR=-frac{dy}{w.mu _{n}.Q1(y)}$$

Here, minus sign is because of to the negative polarity of the inversion layer charge Q1 and μn is the surface mobility, which is constant. Now, substitute the value of Q1(y) in the dR equation −

$$dR=-frac{dy}{w.mu _{n}.left { -C_{ox}left [ V_{GS}-V_{Cleft ( Y appropriate )} appropriate ]-V_{TO} appropriate }}$$

$$dR=frac{dy}{w.mu _{n}.C_{ox}left [ V_{GS}-V_{Cleft ( Y appropriate )} appropriate ]-V_{TO}}$$

Now voltage fall in small dy area can end up being given simply by

$$dV_{c}=I_{D}.dR$$

Put the value of dR in the above equation

$$dV_{C}=I_{D}.frac{dy}{w.mu_{n}.C_{ox}left [ V_{GS}-V_{C(Y)} appropriate ]-V_{TO}}$$

$$w.mu _{n}.C_{ox}left [ V_{GS}-V_{C(Y)}-V_{TO} appropriate ].dV_{C}=I_{D}.dy$$

To obtain the drain current ID over the whole channel area, the above equation can end up being integrated asizey the channel from y = 0 to y = L and voltages VC(y) = 0 to VC(y) = VDS,

$$C_{ox}.w.mu _{n}.int_{V_{c}=0}^{V_{DS}} left [ V_{GS}-V_{Cleft ( Y appropriate )}-V_{TO} appropriate ].dV_{C} = int_{Y=0}^{L}I_{D}.dy$$

$$frac{C_{ox}.w.mu _{n}}{2}left ( 2left [ V_{GS}-V_{TO} appropriate ] V_{DS}-V_{DS}^{2}appropriate ) = I_{D}left [ L-0 appropriate ]$$

$$I_{D} = frac{C_{ox}.mu _{n}}{2}.frac{w}{L}left ( 2left [ V_{GS}-V_{TO} appropriate ]V_{DS}-V_{DS}^{2} appropriate )$$

For collectionar area VDS < VGS − VTO. For saturation area, value of VDS is huger than (VGS − VTO). Therefore, for saturation area VDS = (VGS − VTO).

$$I_{D} = C_{ox}.mu _{n}.frac{w}{2}left ( frac{left [ 2V_{DS} appropriate ]V_{DS}-V_{DS}^{2}}{L} appropriate )$$

$$I_{D} = C_{ox}.mu _{n}.frac{w}{2}left ( frac{2V_{DS}^{2}-V_{DS}^{2}}{L} appropriate )$$

$$I_{D} = C_{ox}.mu _{n}.frac{w}{2}left ( frac{V_{DS}^{2}}{L} appropriate )$$

$$I_{D} = C_{ox}.mu _{n}.frac{w}{2}left ( frac{left [ V_{GS}-V_{TO} appropriate ]^{2}}{L} appropriate )$$

VLSI Design – MOS Inverter

The inverter is truly the nucleus of all digital styles. Once it is operation and properconnects are clearrestr belowstood, styleing more intricate structures such as NAND gates, adders, multiprestrs, and miharvestrocessors is greatly simplified. The electrical end up beinghavior of these complex circuit is can end up being almany kind of comppermitely derived simply by extrapolating the results obtained for inverters.

The analysis of inverters can end up being extended to exnormal the end up beinghavior of more complex gates such as NAND, NOR, or XOR, which in turn form the constructing blocks for modules such as multiprestrs and processors. In this particular particular chapter, we focus on one single incarnation of the inverter gate, end up beinging the static CMOS inverter — or the CMOS inverter, in short. This is particularly the many kind of popular at present and presently correct now therefore deserves our special attention.

Principle of Operation

The logic symbol and truth table of ideal inverter is shown in figure given end up beinglow. Here A is the input and B is the inverted away presently correct now thereput represented simply by their own own node voltages. Using positive logic, the Boolean value of logic 1 is represented simply by Vdd and logic 0 is represented simply by 0. Vth is the inverter threshold voltage, which is Vdd /2, where Vdd is the away presently correct now thereput voltage.

The away presently correct now thereput is switched from 0 to Vdd when input is less than Vth. So, for 0<Vin<Vth away presently correct now thereput is equal to logic 0 input and Vth<Vin< Vdd is equal to logic 1 input for inverter.

Inverter

The charworkioneristics shown in the figure are ideal. The generalized circuit structure of an nMOS inverter is shown in the figure end up beinglow.

Generalized Circuit

From the given figure, we can see thead wear the input voltage of inverter is equal to the gate to source voltage of nMOS transistor and away presently correct now thereput voltage of inverter is equal to drain to source voltage of nMOS transistor. The source to substrate voltage of nMOS is furthermore calimmediateed dwater for transistor which is grounded; so VSS = 0. The away presently correct now thereput node is connected with a lumped capacitance used for VTC.

Resistive Load Inverter

The fundamental structure of a resistive load inverter is shown in the figure given end up beinglow. Here, enhancement kind nMOS workions as the dwater transistor. The load consists of a fundamental collectionar resistor RL. The power supply of the circuit is VDD and the drain current ID is equal to the load current IR.

Resistive Load

Circuit Operation

When the input of the dwater transistor is less than threshold voltage VTH (Vin < VTH), dwater transistor is wislim the cut – away from area and does not conduct any kind of current. So, the voltage fall amix the load resistor is ZERO and away presently correct now thereput voltage is equal to the VDD. Now, when the input voltage incrrerestves further, dwater transistor will start conducting the non-zero current and nMOS goes in saturation area.

Mathematically,

$$I_{D} = frac{K_{n}}{2}left [ V_{GS}-V_{TO} appropriate ]^{2}$$

Increasing the input voltage further, dwater transistor will enter into the collectionar area and away presently correct now thereput of the dwater transistor decrrerestves.

$$I_{D} = frac{K_{n}}{2}2left [ V_{GS}-V_{TO} appropriate ]V_{DS}-V_{DS}^{2}$$

VTC of the resistive load inverter, shown end up beinglow, indicates the operating mode of dwater transistor and voltage points.

Resistive Load Inverter

Inverter with N kind MOSFET Load

The main advantage of using MOSFET as load device is thead wear the silicon area occupied simply by the transistor is smaller than the area occupied simply by the resistive load. Here, MOSFET is workionive load and inverter with workionive load gives a end up beingtter performance than the inverter with resistive load.

Enhancement Load NMOS

Two inverters with enhancement-kind load device are shown in the figure. Load transistor can end up being operated possibly, in saturation area or in collectionar area, depending on the bias voltage apprestd to it is gate terminal. The saturated enhancement load inverter is shown in the fig. (a). It requires a single voltage supply and fundamental fabrication process and so VOH is limited to the VDD − VT.

Enhancement Load NMOS

The collectionar enhancement load inverter is shown in the fig. (b). It always operates in collectionar area; so VOH level is equal to VDD.

Linear load inverter has higher sound margin compared to the saturated enhancement inverter. But, the didepressingvantage of collectionar enhancement inverter is, it requires 2 separate power supply and both the circuit is suffer from high power dissipation. Therefore, enhancement inverters are not used in any kind of huge-dimension digital applications.

Deppermition Load NMOS

Deppermition Load NMOS

Drawbacks of the enhancement load inverter can end up being overcome simply by using deppermition load inverter. Compared to enhancement load inverter, deppermition load inverter requires couple of more fabrication steps for channel implant to adsimply the threshold voltage of load.

The advantages of the deppermition load inverter are – sharp VTC transition, end up beingtter sound margin, single power supply and smaller generall layaway presently correct now there area.

As shown in the figure, the gate and source terminal of load are connected; So, VGS = 0. Thus, the threshold voltage of the load is negative. Hence,

$$V_{GS,load}> V_{T,load}$$ is satisfied

Therefore, load device always has a conduction channel regardless of input and away presently correct now thereput voltage level.

When the load transistor is wislim saturation area, the load current is given simply by

$$I_{D,load} = frac{K_{n,load}}{2}left [ -V_{T,load}left ( V_{away presently correct now there} appropriate ) appropriate ]^{2}$$

When the load transistor is wislim collectionar area, the load current is given simply by

$$I_{D,load} = frac{K_{n,load}}{2}left [ 2left | V_{T,load}left ( V_{away presently correct now there} appropriate ) appropriate |.left ( V_{DD}-V_{away presently correct now there} appropriate )-left ( V_{DD}-V_{away presently correct now there} appropriate )^{2} appropriate ]$$

The voltage transfer charworkioneristics of the deppermition load inverter is shown in the figure given end up beinglow −

VTC of Deppermition Load

CMOS Inverter – Circuit, Operation and Description

The CMOS inverter circuit is shown in the figure. Here, nMOS and pMOS transistors work as dwater transistors; when one transistor is ON, other is OFF.

CMOS Inverter Circuit

This configuration is calimmediateed complementary MOS (CMOS). The input is connected to the gate terminal of both the transistors such thead wear both can end up being driven immediately with input voltages. Substrate of the nMOS is connected to the ground and substrate of the pMOS is connected to the power supply, VDD.

So VSB = 0 for both the transistors.

$$V_{GS,n}=V_{in}$$

$$V_{DS,n}=V_{away presently correct now there}$$

And,

$$V_{GS,p}=V_{in}-V_{DD}$$

$$V_{DS,p}=V_{away presently correct now there}-V_{DD}$$

When the input of nMOS is smaller than the threshold voltage (Vin < VTO,n), the nMOS is cut – away from and pMOS is wislim collectionar area. So, the drain current of both the transistors is zero.

$$I_{D,n}=I_{D,p}=0$$

Therefore, the away presently correct now thereput voltage VOH is equal to the supply voltage.

$$V_{away presently correct now there}=V_{OH}=V_{DD}$$

When the input voltage is greater than the VDD + VTO,p, the pMOS transistor is wislim the cutaway from area and the nMOS is wislim the collectionar area, so the drain current of both the transistors is zero.

$$I_{D,n}=I_{D,p}=0$$

Therefore, the away presently correct now thereput voltage VOL is equal to zero.

$$V_{away presently correct now there}=V_{OL}=0$$

The nMOS operates in the saturation area if Vin > VTO and if folloearng conditions are satisfied.

$$V_{DS,n}geq V_{GS,n}-V_{TO,n} $$

$$V_{away presently correct now there}geq V_{in}-V_{TO,n} $$

The pMOS operates in the saturation area if Vin < VDD + VTO,p and if folloearng conditions are satisfied.

$$V_{DS,p}leq V_{GS,p}-V_{TO,p} $$

$$V_{away presently correct now there}leq V_{in}-V_{TO,p} $$

For various value of input voltages, the operating areas are listed end up beinglow for both transistors.

Region Vin Vaway presently correct now there nMOS pMOS
A < VTO, n VOH Cut – away from Linear
B VIL High ≈ VOH Saturation Linear
C Vth Vth Saturation Saturation
D VIH Low ≈ VOL Linear Saturation
E > (VDD + VTO, p) VOL Linear Cut – away from

The VTC of CMOS is shown in the figure end up beinglow −

VTC of CMOS Inverter

Combinational MOS Logic Circuit is

Combinational logic circuit is or gates, which perform Boolean operations on multiple input variables and figure away the away presently correct now thereputs as Boolean functions of the inputs, are the fundamental constructing blocks of all digital systems. We will examine fundamental circuit configurations such as 2-input NAND and NOR gates and then expand our analysis to more general cases of multiple-input circuit structures.

Next, the CMOS logic circuit is will end up being presented in a similar fashion. We will stress the similariconnects and differences end up beingtween the nMOS deppermition-load logic and CMOS logic circuit is and point away presently correct now there the advantages of CMOS gates with examples. In it is many kind of general form, a combinational logic circuit, or gate, performing a Boolean function can end up being represented as a multiple-input, single-away presently correct now thereput system, as depicted in the figure.

Logic Circuit

Node voltages, referenced to the ground achievable, represent all input variables. Using positive logic convention, the Boolean (or logic) value of "1" can end up being represented simply by a high voltage of VDD, and the Boolean (or logic) value of "0" can end up being represented simply by a low voltage of 0. The away presently correct now thereput node is loaded with a capacitance CL, which represents the combined capacitances of the parasitic device in the circuit.

CMOS Logic Circuit is

CMOS Two input NOR Gate

The circuit consists of a parallel-connected n-net and a series-connected complementary p-net. The input voltages VX and VY are apprestd to the gates of one nMOS and one pMOS transistor.

When possibly one or both inputs are high, i.e., when the n-net generates a conducting route end up beingtween the away presently correct now thereput node and the ground, the p-net is cut—away from. If both input voltages are low, i.e., the n-net is cut-away from, then the p-net generates a conducting route end up beingtween the away presently correct now thereput node and the supply voltage.

For any kind of given input combination, the complementary circuit structure is such thead wear the away presently correct now thereput is connected possibly to VDD or to ground via a low-resistance route and a DC current route end up beingtween the VDD and ground is not established for any kind of input combinations. The away presently correct now thereput voltage of the CMOS, 2 input NOR gate will get a logic-low voltage of VOL = 0 and a logic-high voltage of VOH = VDD. The equation of the switching threshold voltage Vth is given simply by

$$V_{th}left ( NOR2 appropriate ) = frac{V_{T,n}+frac{1}{2}sqrt{frac{k_{p}}{k_{n}}left ( V_{DD}-left | V_{T,p} appropriate | appropriate )}}{1+frac{1}{2}sqrt{frac{k_{p}}{k_{n}}}}$$

Layaway presently correct now there of CMOS 2-input NOR Gate

Layaway presently correct now there of CMOS

The figure shows a sample layaway presently correct now there of CMOS 2-input NOR gate, using single-layer metallic and single-layer polysilicon. The features of this particular particular layaway presently correct now there are −

  • Single vertical polycollections for every input
  • Single workionive forms for N and P devices, respectively
  • Metal buses operatening horizontal

The stick diagram for the CMOS N0R2 gate is shown in the figure given end up beinglow; which corresponds immediately to the layaway presently correct now there, but does not contain W and L information. The diffusion areas are depicted simply by rectangles, the metallic interinterconnections and strong collections and groups, respectively represent contworkions, and the mixhead wearched strips represent the polysilicon columns. Stick diagram is helpful for planning optimum layaway presently correct now there topology.

NOR gate stick diagram

CMOS Two-input NAND Gate

The circuit diagram of the 2 input CMOS NAND gate is given in the figure end up beinglow.

NAND Gate

The principle of operation of the circuit is exworkion dual of the CMOS 2 input NOR operation. The n – net consisting of 2 series connected nMOS transistor generates a conducting route end up beingtween the away presently correct now thereput node and the ground, if both input voltages are logic high. Both of the parallelly connected pMOS transistor in p-net will end up being away from.

For all other input combination, possibly one or both of the pMOS transistor will end up being turn ON, while p – net is cut away from, thus, creating a current route end up beingtween the away presently correct now thereput node and the power supply voltage. The switching threshold for this particular particular gate is obtained as −

$$V_{th}left ( NAND2 appropriate ) = frac{V_{T,n}+2sqrt{frac{k_{p}}{k_{n}}left ( V_{DD}-left | V_{T,p} appropriate | appropriate )}}{1+2sqrt{frac{k_{p}}{k_{n}}}}$$

The features of this particular particular layaway presently correct now there are as follows −

  • Single polysilicon collections for inputs operate vertically amix both N and P workionive areas.
  • Single workionive forms are used for constructing both nMOS devices and both pMOS devices.
  • Power bussing is operatening horizontal amix top and base of layaway presently correct now there.
  • Output cables operates horizontal for easy interinterconnection to neighbouring circuit.

Complex Logic Circuit is

NMOS Deppermition Load Complex Logic Gate

To realize complex functions of multiple input variables, the fundamental circuit structures and style principles generateed for NOR and NAND can end up being extended to complex logic gates. The capability to realize complex logic functions, using a small numend up beingr of transistors is one of the many kind of attrworkionive features of nMOS and CMOS logic circuit is. Conaspectr the folloearng Boolean function as an example.

$$overcollection{Z=Pleft ( S+T appropriate )+QR}$$

The nMOS deppermition-load complex logic gate used to realize this particular particular function is shown in figure. In this particular particular figure, the left nMOS dwater branch of three dwater transistors is used to perform the logic function P (S + T), while the appropriate-hand aspect branch performs the function QR. By connecting the 2 branches in parallel, and simply by placing the load transistor end up beingtween the away presently correct now thereput node and the supply voltage VDD, we obtain the given complex function. Each input variable is assigned to only one dwater.

complex logic gate

Inspection of the circuit topology gives fundamental style principles of the pull-down ne2rk −

  • OR operations are performed simply by parallel-connected dwaters.
  • AND operations are performed simply by series-connected dwaters.
  • Inversion is provided simply by the nature of MOS circuit operation.

If all input variables are logic-high in the circuit realizing the function, the equivalent dwater (W/L) ratio of the pull-down ne2rk consisting of five nMOS transistors is

$$frac{W}{L}=frac{1}{frac{1}{left ( W/L appropriate )Q}+frac{1}{left ( W/L appropriate )R}}+frac{1}{frac{1}{left ( W/L appropriate )P}+frac{1}{left ( W/L appropriate )S+left ( W/L appropriate )Q}}$$

Complex CMOS Logic Gates

The realization of the n-net, or pull-down ne2rk, is based on the exworkion same fundamental style principles examined for nMOS deppermition-load complex logic gate. The pMOS pull-up ne2rk must end up being the dual ne2rk of the n-net.

It means all parallel interinterconnections in the nMOS ne2rk will correspond to a series interinterconnection in the pMOS ne2rk, and all series interinterconnection in the nMOS ne2rk correspond to a parallel interinterconnection in the pMOS ne2rk. The figure shows a fundamental construction of the dual p-net (pull-up) graph from the n-net (pull-down) graph.

Dual Graph Concept

Each dwater transistor in the pull-down ne2rk is shown simply by ai and every node is shown simply by a vertex in the pull-down graph. Next, a brand new vertex is generated wislim every congoodd area in the pull graph, and neighbouring vertices are connected simply by advantages which mix every advantage in the pull-down graph only once. This brand new graph shows the pull-up ne2rk.

Boolean function

Layaway presently correct now there Technique using Euler Graph Method

The figure shows the CMOS implementation of a complex function and it is stick diagram done with arbitrary gate ordering thead wear gives an extremely non-optimum layaway presently correct now there for the CMOS gate.

In this particular particular case, the separation end up beingtween the polysilicon columns must permit diffusion-todiffusion separation in end up beingtween. This particularly consumes a conaspectrably amount of extra silicon area.

complex function
stick diagram

By using the Euler route, we can obtain an optimum layaway presently correct now there. The Euler route is degoodd as an uninterrupted route thead wear traverses every advantage (branch) of the graph exworkionly once. Find Euler route in both the pull-down tree graph and the pull-up tree graph with identical ordering of the inputs.

VLSI Design – Sequential MOS Logic Circuit is

Logic circuit is are divided into 2 categories − (a) Combinational Circuit is, and (b) Sequential Circuit is.

In Combinational circuit is, the away presently correct now thereput depends only on the condition of the lacheck inputs.

In Sequential circuit is, the away presently correct now thereput depends not only on the lacheck inputs, but furthermore on the condition of earrestr inputs. Sequential circuit is contain memory elements.

Classification of Logic Circuit is

Sequential circuit is are of three kinds −

Bistable − Bistable circuit is have 2 stable operating points and will end up being in possibly of the states. Example − Memory cellularulars, latches, flip-flops and registers.

Monostable − Monostable circuit is have only one stable operating point and even if they are temporarily perturend up beingd to the opposite state, they will return in time to their own own stable operating point. Example: Timers, pulse generators.

Astable − circuit is have no stable operating point and oscillate end up beingtween a few states. Example − Ring oscillator.

CMOS Logic Circuit is

SR Latch based on NOR Gate

Gate Level

If the set input (S) is equal to logic "1" and the reset input is equal to logic "0." then the away presently correct now thereput Q will end up being forced to logic "1". While $overcollection{Q}$ is forced to logic "0". This means the SR latch will end up being set, irrespective of it is previous state.

Similarly, if S is equal to "0" and R is equal to "1" then the away presently correct now thereput Q will end up being forced to "0" while $overcollection{Q}$ is forced to "1". This means the latch is reset, regardless of it is previously held state. Finally, if both of the inputs S and R are equal to logic "1" then both away presently correct now thereput will end up being forced to logic "0" which conflicts with the complementarity of Q and $overcollection{Q}$.

Therefore, this particular particular input combination is not permited during normal operation. Truth table of NOR based SR Latch is given in table.

S R Q $overcollection{Q}$ Operation
0 0 Q $overcollection{Q}$ Hold
1 0 1 0 Set
0 1 0 1 Reset
1 1 0 0 Not permited

CMOS SR latch based on NOR gate is shown in the figure given end up beinglow.

CMOS SR latch

If the S is equal to VOH and the R is equal to VOL, both of the parallel-connected transistors M1 and M2 will end up being ON. The voltage on node $overcollection{Q}$ will assume a logic-low level of VOL = 0.

At the exworkion same time, both M3 and M4 are turned away from, which results in a logic-high voltage VOH at node Q. If the R is equal to VOH and the S is equal to VOL, M1 and M2 turned away from and M3 and M4 turned on.

SR Latch based on NAND Gate

SR Latch

Block diagram and gate level schematic of NAND based SR latch is shown in the figure. The small groups at the S and R input terminals represents thead wear the circuit responds to workionive low input signals. The truth table of NAND based SR latch is given in table

S R Q Q′
0 0 NC NC No alter. Latch remained in present state.
1 0 1 0 Latch SET.
0 1 0 1 Latch RESET.
1 1 0 0 Invalid condition.

If S goes to 0 (while R = 1), Q goes high, pulling $overcollection{Q}$ low and the latch enters Set state

S = 0 then Q = 1 (if R = 1)

If R goes to 0 (while S = 1), Q goes high, pulling $overcollection{Q}$ low and the latch is Reset

R = 0 then Q = 1 (if S = 1)

Hold state requires both S and R to end up being high. If S = R = 0 then away presently correct now thereput is not permited, as it would result in an indeterminate state. CMOS SR Latch based on NAND Gate is shown in figure.

CMOS on NAND gate

Deppermition-load nMOS SR Latch based on NAND Gate is shown in figure. The operation is similar to thead wear of CMOS NAND SR latch. The CMOS circuit implementation has low static power dissipation and high sound margin.

CMOS Logic Circuit is

Clocked SR Latch

The figure shows a NOR-based SR latch with a clock added. The latch is responsive to inputs S and R only when CLK is high.

Clocked SR Latch

When CLK is low, the latch retains it is current state. Observe thead wear Q alters state −

  • When S goes high during positive CLK.
  • On leading CLK advantage after alters in S & R during CLK low time.
  • A positive glitch in S while CLK is high
  • When R goes high during positive CLK.

implementation of clocked NOR

CMOS AOI implementation of clocked NOR based SR latch is shown in the figure. Note thead wear only 12 transistors required.

  • When CLK is low, 2 series terminals in N tree N are open up and 2 parallel transistors in tree P are ON, thus retaining state in the memory cellularular.

  • When clock is high, the circuit end up beingcomes simply a NOR based CMOS latch which will respond to input S and R.

Clocked SR Latch based on NAND Gate

based on NAND Gate

Circuit is implemented with four NAND gates. If this particular particular circuit is implemented with CMOS then it requires 16 transistors.

  • The latch is responsive to S or R only if CLK is high.
  • If both input signals and the CLK signals are workionive high: i.e., the latch away presently correct now thereput Q will end up being set when CLK = "1" S = "1" and R = "0"
  • Similarly, the latch will end up being reset when CLK = "1," S = "0," and

When CLK is low, the latch retains it is present state.

Clocked JK Latch

Clocked JK

The figure above shows a clocked JK latch, based on NAND gates. The didepressingvantage of an SR latch is thead wear when both S and R are high, it is away presently correct now thereput state end up beingcomes indeterminant. The JK latch eliminates this particular particular problem simply by using give food toback from away presently correct now thereput to input, such thead wear all input states of the truth table are permitable. If J = K = 0, the latch will hold it is present state.

If J = 1 and K = 0, the latch will set on the next positive-going clock advantage, i.e. Q = 1, $overcollection{Q}$ = 0

If J = 0 and K = 1, the latch will reset on the next positive-going clock advantage, i.e. Q = 1 and $overcollection{Q}$ = 0.

If J = K = 1, the latch will toggle on the next positive-going clock advantage

The operation of the clocked JK latch is summarized in the truth table given in table.

J

K

Q

$overcollection{Q}$

S

R

Q

$overcollection{Q}$

Operation

0 0 0 1 1 1 0 1 Hold
1 0 1 1 1 0
0 1 0 1 1 1 0 1 Reset
1 0 1 0 0 1
1 0 0 1 0 1 1 0 Set
1 0 1 1 1 0
1 1 0 1 0 1 1 0 toggle
1 0 1 0 0 1

CMOS D Latch Implementation

CMOS Gate level
CMOS D Latch

The D latch is normally, implemented with transmission gate (TG) switches as shown in the figure. The input TG is workionivated with CLK while the latch give food toback loop TG is workionivated with CLK. Input D is accepted when CLK is high. When CLK goes low, the input is open upcircuited and the latch is set with the prior data D.

VLSI Design – VHDL Introduction

VHDL stands for very high-speed integrated circuit hardware description language. It is a programming language used to model a digital system simply by dataflow, end up beinghavioral and structural style of modeling. This language was preliminary introduced in 1981 for the department of Defense (DoD) below the VHSIC program.

Describing a Design

In VHDL an entity is used to descriend up being a hardware module. An entity can end up being descriend up beingd using,

  • Entity declaration
  • Architecture
  • Configuration
  • Package declaration
  • Package body

Let’s see exworkly whead wear are these?

Entity Declaration

It degoods the names, input away presently correct now thereput signals and modes of a hardware module.

Syntax

entity entity_name is
   Port declaration;
end entity_name;

An entity declaration need to start with ‘entity’ and end with ‘end’ keywords. The immediateion will end up being input, away presently correct now thereput or inaway presently correct now there.

In Port can end up being read
Out Port can end up being generated
Inaway presently correct now there Port can end up being read and generated
Buffer Port can end up being read and generated, it can have only one source.

Architecture

Architecture can end up being descriend up beingd using structural, dataflow, end up beinghavioral or mixed style.

Syntax

architecture architecture_name of entity_name 
architecture_declarative_part;

end up beinggin
   Statements;
end architecture_name;

Here, we need to specify the entity name for which we are writing the architecture body. The architecture statements need to end up being inaspect the ‘end up beinggin’ and ‘énd’ keyword. Architecture declarative part may contain variables, constants, or component declaration.

Data Flow Modeling

In this particular particular modeling style, the flow of data through the entity is expressed using concurrent (parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.

Beaspects them, assignments using only operators (AND, NOT, +, *, sll, etc.) can furthermore end up being used to construct code.

Finally, a special kind of assignment, calimmediateed BLOCK, can furthermore end up being employed in this particular particular kind of code.

In concurrent code, the folloearng can end up being used −

  • Operators
  • The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
  • The GENERATE statement;
  • The BLOCK statement

Behavioral Modeling

In this particular particular modeling style, the end up beinghavior of an entity as set of statements is executed sequentially in the specified order. Only statements placed inaspect a PROCESS, FUNCTION, or PROCEDURE are sequential.

PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code thead wear are executed sequentially.

However, as a whole, any kind of of these blocks is still concurrent with any kind of other statements placed away presently correct now there’aspect it.

One imslotant aspect of end up beinghavior code is thead wear it is not limited to sequential logic. Indeed, with it, we can construct sequential circuit is as well as combinational circuit is.

The end up beinghavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are furthermore rerigided and they are supposed to end up being used in sequential code only. VARIABLE can never end up being global, so it is value cannot end up being comppermiteed away presently correct now there immediately.

Structural Modeling

In this particular particular modeling, an entity is descriend up beingd as a set of interconnected components. A component immediateiation statement is a concurrent statement. Therefore, the order of these statements is not imslotant. The structural style of modeling descriend up beings only an interinterinterconnection of components (watched as black containeres), withaway presently correct now there implying any kind of end up beinghavior of the components themselves nor of the entity thead wear they collectively represent.

In Structural modeling, architecture body is composed of 2 parts − the declarative part (end up beingfore the keyword end up beinggin) and the statement part (after the keyword end up beinggin).

Logic Operation – AND GATE

AND GATE

X Y Z
0 0 0
0 1 0
1 0 0
1 1 1
VHDL Code:
Library ieee;
use ieee.std_logic_1164.all;

entity and1 is
   slot(x,y:in bit ; z:away presently correct now there bit);
end and1;

architecture virat of and1 is
end up beinggin
   z<=x and y; 
end virat;

Waveforms

Waveforms AND

Logic Operation – OR Gate

OR GATE

X Y Z
0 0 0
0 1 1
1 0 1
1 1 1
VHDL Code: 
Library ieee; 
use ieee.std_logic_1164.all;  

entity or1 is
   slot(x,y:in bit ; z:away presently correct now there bit); 
end or1; 
 
architecture virat of or1 is
end up beinggin
   z<=x or y; 
end virat;

Waveforms

Waveforms OR

Logic Operation – NOT Gate

NOT GATE

X Y
0 1
1 0
VHDL Code:
  
Library ieee; 
use ieee.std_logic_1164.all; 
 
entity not1 is
   slot(x:in bit ; y:away presently correct now there bit); 
end not1; 
 
architecture virat of not1 is
end up beinggin
   y<=not x;
end virat; 

Waveforms

Waveforms Not

Logic Operation – NAND Gate

NAND GATE

X Y z
0 0 1
0 1 1
1 0 0
1 1 0
VHDL Code:
  
Library ieee; 
use ieee.std_logic_1164.all; 

entity nand1 is
   slot(a,b:in bit ; c:away presently correct now there bit); 
end nand1; 
 
architecture virat of nand1 is
end up beinggin
   c<=a nand b; 
end virat; 

Waveforms

Waveforms NAND

Logic Operation – NOR Gate

NOR GATE

X Y z
0 0 1
0 1 0
1 0 0
1 1 0
VHDL Code: 
 
Library ieee; 
use ieee.std_logic_1164.all; 
 
entity nor1 is
   slot(a,b:in bit ; c:away presently correct now there bit); 
end nor1; 
 
architecture virat of nor1 is
end up beinggin
   c<=a nor b;
end virat; 

Waveforms

Waveforms NOR

Logic Operation – XOR Gate

XOR GATE

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code: 
 
Library ieee; 
use ieee.std_logic_1164.all;
  
entity xor1 is
   slot(a,b:in bit ; c:away presently correct now there bit); 
end xor1;
  
architecture virat of xor1 is
end up beinggin
   c<=a xor b; 
end virat;

Waveforms

Waveforms XOR

Logic Operation – X-NOR Gate

X Y Z
0 0 1
0 1 1
1 0 1
1 1 0
VHDL Code: 
 
Library ieee; 
use ieee.std_logic_1164.all; 

entity xnor1 is
   slot(a,b:in bit ; c:away presently correct now there bit); 
end xnor1; 
 
architecture virat of xnor1 is
end up beinggin
   c<=not(a xor b); 
end virat;

Waveforms

Waveforms X-NOR

VHDL Programming Combinational Circuit is

This chapter exnormals the VHDL programming for Combinational Circuit is.

VHDL Code for a Half-Adder

VHDL Code:
  
Library ieee; 
use ieee.std_logic_1164.all;
  
entity half_adder is
   slot(a,b:in bit; sum,carry:away presently correct now there bit); 
end half_adder; 
 
architecture data of half_adder is
end up beinggin
   sum<= a xor b;  
   carry <= a and b;  
end data; 

Waveforms

Half-Adder

VHDL Code for a Full Adder

Library ieee; 
use ieee.std_logic_1164.all;
 
entity comppermite_adder is slot(a,b,c:in bit; sum,carry:away presently correct now there bit); 
end comppermite_adder;
  
architecture data of comppermite_adder is
end up beinggin
   sum<= a xor b xor c; 
   carry <= ((a and b) or (b and c) or (a and c)); 
end data;

Waveforms

Full Adder

VHDL Code for a Half-Subtrworkionor

Library ieee;
use ieee.std_logic_1164.all;
  
entity half_sub is
   slot(a,c:in bit; d,b:away presently correct now there bit);
end half_sub;  

architecture data of half_sub is
end up beinggin
   d<= a xor c;
   b<= (a and (not c));
end data;

Waveforms

Half-Subtrworkionor

VHDL Code for a Full Subtrworkionor

Library ieee; 
use ieee.std_logic_1164.all;
  
entity comppermite_sub is
   slot(a,b,c:in bit; sub,borrange:away presently correct now there bit); 
end comppermite_sub; 
 
architecture data of comppermite_sub is
end up beinggin
   sub<= a xor b xor c; 
   borrange <= ((b xor c) and (not a)) or (b and c); 
end data; 

Waveforms

Full Subtrworkionor

VHDL Code for a Multiplexer

Library ieee; 
use ieee.std_logic_1164.all;
  
entity mux is
   slot(S1,S0,D0,D1,D2,D3:in bit; Y:away presently correct now there bit);
end mux;
  
architecture data of mux is
end up beinggin 
   Y<= (not S0 and not S1 and D0) or 
      (S0 and not S1 and D1) or 
      (not S0 and S1 and D2) or
      (S0 and S1 and D3); 
end data;

Waveforms

Multiplexer

VHDL Code for a Demultiplexer

Library ieee; 
use ieee.std_logic_1164.all;
  
entity demux is
   slot(S1,S0,D:in bit; Y0,Y1,Y2,Y3:away presently correct now there bit); 
end demux;
  
architecture data of demux is
end up beinggin 
   Y0<=  ((Not S0) and (Not S1) and D); 
   Y1<=  ((Not S0) and S1 and D); 
   Y2<=  (S0 and (Not S1) and D); 
   Y3<=  (S0 and S1 and D); 
end data;

Waveforms

Demultiplexer

VHDL Code for a 8 x 3 Encoder

library ieee; 
use ieee.std_logic_1164.all; 
 
entity enc is
   slot(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: away presently correct now there bit); 
end enc; 
 
architecture vcgandhi of enc is
end up beinggin 
   o0<=i4 or i5 or i6 or i7; 
   o1<=i2 or i3 or i6 or i7; 
   o2<=i1 or i3 or i5 or i7; 
end vcgandhi;

Waveforms

Encoder

VHDL Code for a 3 x 8 Decoder

library ieee; 
use ieee.std_logic_1164.all;

entity dec is
   slot(i0,i1,i2:in bit; o0,o1,o2,o3,o4,o5,o6,o7: away presently correct now there bit); 
end dec; 
 
architecture vcgandhi of dec is
end up beinggin 
   o0<=(not i0) and (not i1) and (not i2); 
   o1<=(not i0) and (not i1) and i2; 
   o2<=(not i0) and i1 and (not i2); 
   o3<=(not i0) and i1 and i2; 
   o4<=i0 and (not i1) and (not i2); 
   o5<=i0 and (not i1) and i2; 
   o6<=i0 and i1 and (not i2); 
   o7<=i0 and i1 and i2; 
end vcgandhi;

Waveforms

Decoder

VHDL Code – 4 bit Parallel adder

library IEEE; 
use IEEE.STD_LOGIC_1164.all;
  
entity pa is
   slot(a : in STD_LOGIC_VECTOR(3 downto 0);
      b : in STD_LOGIC_VECTOR(3 downto 0);
      ca : away presently correct now there STD_LOGIC;
      sum : away presently correct now there STD_LOGIC_VECTOR(3 downto 0) 
   ); 
end pa; 
 
architecture vcgandhi of pa is
   Component fa is
      slot (a : in STD_LOGIC; 
         b : in STD_LOGIC; 
         c : in STD_LOGIC; 
         sum : away presently correct now there STD_LOGIC; 
         ca : away presently correct now there STD_LOGIC
      ); 
   end component;         
   signal s : std_logic_vector (2 downto 0); 
   signal temp: std_logic;
end up beinggin 
   temp<='0'; 
   u0 : fa slot map (a(0),b(0),temp,sum(0),s(0)); 
   u1 : fa slot map (a(1),b(1),s(0),sum(1),s(1)); 
   u2 : fa slot map (a(2),b(2),s(1),sum(2),s(2));
   ue : fa slot map (a(3),b(3),s(2),sum(3),ca);  
end vcgandhi;

Waveforms

Parallel adder

VHDL Code – 4 bit Parity Checker

library ieee; 
use ieee.std_logic_1164.all; 
 
entity parity_checker is 
   slot (a0,a1,a2,a3 : in std_logic; 
      p : away presently correct now there std_logic); 
end parity_checker;  

architecture vcgandhi of parity_checker is 
end up beinggin    
   p <= (((a0 xor a1) xor a2) xor a3); 
end vcgandhi;

Waveforms

Parity Checker

VHDL Code – 4 bit Parity Generator

library ieee;
use ieee.std_logic_1164.all;

entity paritygen is
   slot (a0, a1, a2, a3: in std_logic; p_odd, p_even: away presently correct now there std_logic);
end paritygen;  

architecture vcgandhi of paritygen is
end up beinggin
   process (a0, a1, a2, a3)
   
	if (a0 ='0' and a1 ='0' and a2 ='0' and a3 =’0’)
      then odd_away presently correct now there <= "0";
      even_away presently correct now there <= "0";
   else
      p_odd <= (((a0 xor a1) xor a2) xor a3);
      p_even <= not(((a0 xor a1) xor a2) xor a3);  
end vcgandhi

Waveforms

Parity Generator

VHDL Programming for Sequential Circuit is

This chapter exnormals how to do VHDL programming for Sequential Circuit is.

VHDL Code for an SR Latch

library ieee; 
use ieee.std_logic_1164.all;
  
entity srl is 
   slot(r,s:in bit; q,qbar:buffer bit); 
end srl;  

architecture virat of srl is 
   signal s1,r1:bit; 
end up beinggin 
   q<= s nand qbar; 
   qbar<= r nand q; 
end virat; 

Waveforms

SR Latch

VHDL Code for a D Latch

library ieee; 
use ieee.std_logic_1164.all;

entity Dl is 
   slot(d:in bit; q,qbar:buffer bit); 
end Dl; 
 
architecture virat of Dl is 
   signal s1,r1:bit; 
end up beinggin 
   q<= d nand qbar; 
   qbar<= d nand q; 
end virat; 

Waveforms

D Latch

VHDL Code for an SR Flip Flop

library ieee; 
use ieee.std_logic_1164.all;
  
entity srflip is 
   slot(r,s,clk:in bit; q,qbar:buffer bit); 
end srflip;
  
architecture virat of srflip is 
   signal s1,r1:bit; 
end up beinggin 
   s1<=s nand clk; 
   r1<=r nand clk;
   q<= s1 nand qbar;
   qbar<= r1 nand q;
end virat;    

Waveforms

SR Flip Flop

VHDL code for a JK Flip Flop

library IEEE; 
use IEEE.STD_LOGIC_1164.all;  

entity jk is 
   slot(
      j : in STD_LOGIC; 
      k : in STD_LOGIC; 
      clk : in STD_LOGIC; 
      reset : in STD_LOGIC; 
      q : away presently correct now there STD_LOGIC; 
      qb : away presently correct now there STD_LOGIC 
   ); 
end jk;
  
architecture virat of jk is 
end up beinggin 
   jkff : process (j,k,clk,reset) is 
   variable m : std_logic := '0'; 
   
   end up beinggin 
      if (reset = '1') then 
         m : = '0'; 
      elsif (rising_advantage (clk)) then 
         if (j/ = k) then
            m : = j; 
         elsif (j = '1' and k = '1') then 
            m : = not m; 
         end if; 
      end if; 
      
      q <= m; 
      qb <= not m; 
   end process jkff; 
end virat;

Waveforms

JK Flip Flop

VHDL Code for a D Flip Flop

Library ieee; 
use ieee.std_logic_1164.all;  

entity dflip is 
   slot(d,clk:in bit; q,qbar:buffer bit); 
end dflip; 
 
architecture virat of dflip is 
   signal d1,d2:bit; 
end up beinggin 
   d1<=d nand clk; 
   d2<=(not d) nand clk; 
   q<= d1 nand qbar; 
   qbar<= d2 nand q; 
end virat;

Waveforms

D Flip Flop

VHDL Code for a T Flip Flop

library IEEE; 
use IEEE.STD_LOGIC_1164.all;  

entity Toggle_flip_flop is 
   slot( 
      t : in STD_LOGIC; 
      clk : in STD_LOGIC; 
      reset : in STD_LOGIC; 
      daway presently correct now there : away presently correct now there STD_LOGIC
   ); 
end Toggle_flip_flop;  

architecture virat of Toggle_flip_flop is 
end up beinggin 
   tff : process (t,clk,reset) is 
   variable m : std_logic : = '0'; 
   
   end up beinggin 
      if (reset = '1') then 
         m : = '0'; 
      elsif (rising_advantage (clk)) then 
         if (t = '1') then 
            m : = not m;        
         end if; 
      end if; 
      daway presently correct now there < = m; 
   end process tff; 
end virat; 

Waveforms

T Flip Flop

VHDL Code for a 4 – bit Up Counter

library IEEE; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
  
entity counter is 
   slot(Clock, CLR : in std_logic; 
      Q : away presently correct now there std_logic_vector(3 downto 0)
   ); 
end counter;  

architecture virat of counter is 
   signal tmp: std_logic_vector(3 downto 0); 
end up beinggin 
   process (Clock, CLR) 
   
   end up beinggin 
      if (CLR = '1') then 
         tmp < = "0000"; 
      elsif (Clock'event and Clock = '1') then 
         mp <= tmp + 1; 
      end if; 
   end process; 
   Q <= tmp; 
end virat;

Waveforms

4 - bit Up Counter

VHDL Code for a 4-bit Down Counter

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all;
  
entity dcounter is 
   slot(Clock, CLR : in std_logic; 
      Q : away presently correct now there std_logic_vector(3 downto 0)); 
end dcounter; 
 
architecture virat of dcounter is 
   signal tmp: std_logic_vector(3 downto 0); 

end up beinggin 
   process (Clock, CLR) 
   end up beinggin 
      if (CLR = '1') then 
         tmp <= "1111"; 
      elsif (Clock'event and Clock = '1') then 
         tmp <= tmp - 1; 
      end if; 
   end process; 
   Q <= tmp; 
end virat;

Waveforms

4-bit Down Counter

VLSI Design – Verilog Introduction

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a digital system like a ne2rk switch or a miharvestrocessor or a memory or a flip−flop. It means, simply by using a HDL we can descriend up being any kind of digital hardware at any kind of level. Designs, which are descriend up beingd in HDL are independent of technology, very easy for styleing and debugging, and are normally more helpful than schematics, particularly for huge circuit is.

Verilog supslots a style at many kind of levels of abstrworkionion. The major three are −

  • Behavioral level
  • Register-transfer level
  • Gate level

Behavioral level

This level descriend up beings a system simply by concurrent algorithms (Behavioural). Every algorithm is sequential, which means it consists of a set of instructions thead wear are executed one simply by one. Functions, tasks and blocks are the main elements. There is no regard to the structural realization of the style.

Register−Transfer Level

Designs using the Register−Transfer Level specify the charworkioneristics of a circuit using operations and the transfer of data end up beingtween the registers. Modern definition of an RTL code is "Any code thead wear is synthesizable is calimmediateed RTL code".

Gate Level

Wislim the logical level, the charworkioneristics of a system are descriend up beingd simply by logical links and their own own timing properconnects. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predegoodd logic primitives (fundamental gates). Gate level modelling may not end up being a appropriate idea for logic style. Gate level code is generated using tools like synthesis tools and his netlist is used for gate level simulation and for backend.

Lexical Tokens

Verilog language source text files are a stream of lexical tokens. A token consists of one or more charworkioners, and every single charworkioner is wislim exworkionly one token.

The fundamental lexical tokens used simply by the Verilog HDL are similar to those in C Programming Language. Verilog is case sensitive. All the key words are in lower case.

White Space

White spaces can contain charworkioners for spaces, tabs, brand new-collections and form give food tos. These charworkioners are ignored other than when they serve to separate tokens.

White space charworkioners are Blank space, Tabs, Carriage returns, New collection, and Form give food tos.

Comments

There are 2 forms to represent the comments

  • 1) Single collection comments end up beinggin with the token // and end with carriage return.

Ex.: //this particular particular is single collection syntax

  • 2) Multicollection comments end up beinggins with the token /* and end with token */

Ex.: /* this particular particular is multicollection Syntax*/

Numend up beingrs

You can specify a numend up beingr in binary, octal, decimal or hexadecimal format. Negative numend up beingrs are represented in 2’s compliment numend up beingrs. Verilog permit is integers, real numend up beingrs and signed & unsigned numend up beingrs.

The syntax is given simply by − <dimension> <radix> <value>

Size or undimensiond numend up beingr can end up being degoodd in <Size> and <radix> degoods whether it is binary, octal, hexadecimal or decimal.

Identifiers

Identifier is the name used to degood the object, such as a function, module or register. Identifiers need to end up beinggin with an alphaend up beingtical charworkioners or belowscore charworkioners. Ex. A_Z, a_z,_

Identifiers are a combination of alphaend up beingtic, numeric, belowscore and $ charworkioners. They can end up being up to 1024 charworkioners sizey.

Operators

Operators are special charworkioners used to put conditions or to operate the variables. There are one, 2 and a couple oftimes three charworkioners used to perform operations on variables.

Ex. >, +, ~, &! =.

Verilog Keywords

Words thead wear have special meaning in Verilog are calimmediateed the Verilog keywords. For example, assign, case, while, cable, reg, and, or, nand, and module. They need to not end up being used as identifiers. Verilog keywords furthermore include compiler immediateives, and system tasks and functions.

Gate Level Modelling

Verilog has built-in primitives like logic gates, transmission gates and switches. These are rarely used for style work but they are used in post synthesis world for modelling of ASIC/FPGA cellularulars.

Gate level modelling exhibit is 2 properconnects −

Drive strength − The strength of the away presently correct now thereput gates is degoodd simply by drive strength. The away presently correct now thereput is strongest if presently correct now there is a immediate interinterconnection to the source. The strength decrrerestves if the interinterconnection is via a conducting transistor and minimumern when connected via a pull-up/down resistive. The drive strength is usually not specified, in which case the strengths defaults to strong1 and strong0.

Delays − If delays are not specified, then the gates do not have propagation delays; if 2 delays are specified, then preliminary one represents the rise delay and the 2nd one, fall delay; if only one delay is specified, then both, rise and fall are equal. Delays can end up being ignored in synthesis.

Gate Primitives

The fundamental logic gates using one away presently correct now thereput and many kind of inputs are used in Verilog. GATE uses one of the keywords – and, nand, or, nor, xor, xnor for use in Verilog for N numend up beingr of inputs and 1 away presently correct now thereput.

Example:  
   Module gate() 
   Wire ot0; 
   Wire ot1; 
   Wire ot2; 
   
   Reg in0,in1,in2,in3; 
   Not U1(ot0,in0); 
   Xor U2(ot1,in1,in2,in3); 
   And U3(ot2, in2,in3,in0) 

Transmission Gate Primitives

Transmission gate primitives include both, buffers and inverters. They have single input and one or more away presently correct now thereputs. In the gate immediateiation syntax shown end up beinglow, GATE stands for possibly the keyword buf or NOT gate.

Example: Not, buf, bufif0, bufif1, notif0, notif1

Not – n away presently correct now thereaway presently correct now there inverter

Buf – n away presently correct now thereput buffer

Bufifo – tristate buffer, workionive low enable

Bufif1 – tristate buffer, workionive high enable

Notifo – tristate inverter, workionive low enable

Notif1 – tristate inverter, workionive high enable

Example:  
   Module gate() 
   Wire away presently correct now there0; 
   Wire away presently correct now there1; 
   
   Reg in0,in1;
   Not U1(away presently correct now there0,in0); 
   Buf U2(away presently correct now there0,in0); 

Data Types

Value Set

Verilog consists of, mainly, four fundamental values. All Verilog data kinds, which are used in Verilog store these values −

0 (logic zero, or false condition)

1 (logic one, or true condition)

x (unbelowstandn logic value)

z (high impedance state)

use of x and z is very limited for synthesis.

Wire

A cable is used to represent a physical cable in a circuit and it is used for interinterconnection of gates or modules. The value of a cable can only end up being read and not assigned in a function or block. A cable cannot store value but is always driven simply by a continuous assignment statement or simply by connecting cable to away presently correct now thereput of a gate/module. Other specific kinds of cables are −

Wand (cabimmediateed-AND) − here value of Wand is dependent on logical AND of all the device dwaters connected to it.

Wor (cabimmediateed-OR) − here value of a Wor is dependent on logical OR of all the device dwaters connected to it.

Tri (three-state) − here all dwaters connected to a tri must end up being z, other than only one (which figure aways value of tri).

Example: 
   Wire [msb:lsb] cable_variable_list; 
   Wirec // fundamental cable 
   Wand d; 
   
   Assign d = a; // value of d is the logical AND of 
   Assign d = b; // a and b 
   Wire [9:0] A; // a cable (vector) of 10 cables. 
   
   Wand [msb:lsb] wand_variable_list; 
   Wor [msb:lsb] wor_variable_list; 
   Tri [msb:lsb] tri_variable_list; 

Register

A reg (register) is a data object, which is holding the value from one procedural assignment to next one and are used only in various functions and procedural blocks. A reg is a fundamental Verilog, variable-kind register and can’t imply a physical register. In multi-bit registers, the data is stored in the form of unsigned numend up beingrs and sign extension is not used.

Example −

reg c; // single 1-bit register variable

reg [5:0] gem; // a 6-bit vector;

reg [6:0] d, e; // 2 7-bit variables

Input, Output, Inaway presently correct now there

These keywords are used to declare input, away presently correct now thereput and biimmediateional slots of a task or module. Here input and inaway presently correct now there slots, which are of cable kind and away presently correct now thereput slot is configured to end up being of cable, reg, wand, wor or tri kind. Always, default is cable kind.

Example

Module sample(a, c, b, d);  
Input c;   // An input where cable is used. 

Output a, b;  // Two away presently correct now thereputs where cable is used. 
Output [2:0] d;  /* A three-bit away presently correct now thereput. One must declare kind in a separate statement. */ 
reg [1:0] a;  // The above ‘a’ slot is for declaration in reg.

Integer

Integers are used in general-purpose variables. They are used mainly in loops-indicies, constants, and parameters. They are of ‘reg’ kind data kind. They store data as signed numend up beingrs whereas explicitly declared reg kinds store them as an unsigned data. If the integer is not degoodd at the time of compiling, then the default dimension would end up being 32 bit is.

If an integer holds a constant, the synthedimensionr adsimplys them to the minimum width needed at the time of compilation.

Example

Integer c;   // single 32-bit integer 
Assign a = 63;  // 63 defaults to a 7-bit variable. 

Supply0, Supply1

Supply0 degood cables connectd to logic 0 (ground) and supply1 degood cables connectd to logic 1 (power).

Example

supply0 logic_0_cables; 
supply0 gnd1;  // equivalent to a cable assigned as 0 

supply1 logic_1_cables; 
supply1 c, s;

Time

Time is a 64-bit quantity thead wear can end up being used in conjunction with the $time system task to hold simulation time. Time is not supsloted for synthesis and hence is used only for simulation purposes.

Example

time time_variable_list; 
time c; 
c = $time;   //c = current simulation time

Parameter

A parameter is defining a constant which can end up being set when you use a module, which permit is customization of module during the immediateiation process.

Example 
Parameter add = 3’b010, sub = 2’b11; 
Parameter n = 3; 
Parameter [2:0] param2 = 3’b110; 

reg [n-1:0] jam; /* A 3-bit register with dimension of n or above. */ 
always @(z) 
y = {{(add - sub){z}};  

if (z)
end up beinggin 
   state = param2[1];
else
   state = param2[2]; 
end 

Operators

Arithmetic Operators

These operators is perform arithmetic operations. The + and −are used as possibly unary (x) or binary (z−y) operators.

The Operators which are included in arithmetic operation are −

+ (addition), −(consider awayionion), * (multiplication), / (division), % (modulus)

Example

parameter v = 5;
reg[3:0] b, d, h, i, count; 
h = b + d; 
i = d - v; 
cnt = (cnt +1)%16; //Can count 0 thru 15.

Relational Operators

These operators compare 2 operands and return the result in a single bit, 1 or 0.

Wire and reg variables are positive. Thus (−3’d001) = = 3’d111 and (−3b001)>3b110.

The Operators which are included in relational operation are −

  • == (equal to)
  • != (not equal to)
  • > (greater than)
  • >= (greater than or equal to)
  • < (less than)
  • <= (less than or equal to)

Example

if (z = = y) c = 1; 
   else c = 0; // Compare in 2’s compliment; d>b 
reg [3:0] d,b; 

if (d[3]= = b[3]) d[2:0] > b[2:0]; 
   else b[3]; 
Equivalent Statement 
e = (z == y);

Bit-wise Operators

Bit-wise operators which are doing a little-simply by-bit comparison end up beingtween 2 operands.

The Operators which are included in Bit wise operation are −

  • & (bitwise AND)
  • | (bitwiseOR)
  • ~ (bitwise NOT)
  • ^ (bitwise XOR)
  • ~^ or ^~(bitwise XNOR)

Example

module and2 (d, b, c); 
input [1:0] d, b; 
away presently correct now thereput [1:0] c; 
assign c = d & b; 
end module 

Logical Operators

Logical operators are bit-wise operators and are used only for single-bit operands. They return a single bit value, 0 or 1. They can work on integers or group of bit is, expressions and treat all non-zero values as 1. Logical operators are generally, used in conditional statements since they work with expressions.

The operators which are included in Logical operation are −

  • ! (logical NOT)
  • && (logical AND)
  • || (logical OR)

Example

cable[7:0] a, b, c; // a, b and c are multibit variables. 
reg x; 

if ((a == b) && (c)) x = 1; //x = 1 if x equals b, and c is nonzero. 
   else x = !a; // x =0 if a is any kind ofslimg but zero.

Reduction Operators

Reduction operators are the unary form of the bitwise operators and operate on all the bit is of an operand vector. These furthermore return a single-bit value.

The operators which are included in Reduction operation are −

  • & (reduction AND)
  • | (reduction OR)
  • ~& (reduction NAND)
  • ~| (reduction NOR)
  • ^ (reduction XOR)
  • ~^ or ^~(reduction XNOR)

Example

Module chk_zero (x, z); 

Input [2:0] x; 
Output z; 
Assign z = & x; // Reduction AND 
End module

Shift Operators

Shift operators, which are shifting the preliminary operand simply by the numend up beingr of bit is specified simply by 2nd operand in the syntax. Vacan’t positions are filimmediateed with zeros for both immediateions, left and appropriate shifts (There is no use sign extension).

The Operators which are included in Shift operation are −

  • << (shift left)
  • >> (shift appropriate)

Example

Assign z = c << 3; /* z = c shifted left 3 bit is;

Vacan’t positions are filimmediateed with 0’s */

Concatenation Operator

The concatenation operator combines 2 or more operands to form a huger vector.

The operator included in Concatenation operation is − { }(concatenation)

Example

cable [1:0] a, h; cable [2:0] x; cable [3;0] y, Z; 
assign x = {1’b0, a}; // x[2] = 0, x[1] = a[1], x[0] = a[0] 
assign b = {a, h}; /* b[3] = a[1], b[2] = a[0], b[1] = h[1], 
b[0] = h[0] */ 
assign {caway presently correct now there, b} = x + Z; // Concatenation of a result 

Replication Operator

The replication operator are macalifornia king multiple copies of an item.

The operator used in Replication operation is − {n{item}} (n fold replication of an item)

Example

Wire [1:0] a, f; cable [4:0] x; 
Assign x = {2{1’f0}, a}; // Equivalent to x = {0,0,a } 
Assign y = {2{a}, 3{f}}; //Equivalent to y = {a,a,f,f} 
For synthesis, Synopsis did absolutely noslimg like a zero replication.

For example:- 
Parameter l = 5, k = 5; 
Assign x = {(l-k){a}}

Conditional Operator

Conditional operator synthedimensions to a multiplexer. It is the exworkion same kind as is used in C/C++ and evaluates one of the 2 expressions based on the condition.

The operator used in Conditional operation is −

(Condition) ? (Result if condition true) −

(result if condition false)

Example

Assign x = (g) ? a : b; 
Assign x = (inc = = 2) ? x+1 : x-1; 
/* if (inc), x = x+1, else x = x-1 */ 

Operands

Literals

Literals are constant-valued operands thead wear are used in Verilog expressions. The 2 commonly used Verilog literals are −

  • String − A string literal operand is a one-dimensional array of charworkioners, which are enshut upd in double quotes (" ").

  • Numeric − A constant numend up beingr operand is specified in binary, octal, decimal or hexadecimal Numend up beingr.

Example

n − integer representing numend up beingr of bit is

F − one of four achievable base formats −

b for binary, o for octal, d for decimal, h for hexadecimal.

“time is”  // string literal 
267        // 32-bit decimal numend up beingr 
2’b01      // 2-bit binary 
20’hB36F   // 20-bit hexadecimal numend up beingr 
‘062       // 32-bit octal numend up beingr 

Wires, Regs, and Parameters

Wires, regs and parameters are the data kinds used as operands in Verilog expressions.

Bit-Selection “x[2]” and Part-Selection “x[4:2]”

Bit-selects and part-selects are used to select one bit and a multiple bit is, respectively, from a cable, reg or parameter vector with the use of square brackets “[ ]”. Bit-selects and part-selects are furthermore used as operands in expressions in the exworkion same way thead wear their own own main data objects are used.

Example

reg [7:0] x, y; 
reg [3:0] z; 
reg a; 
a = x[7] & y[7];      // bit-selects 
z = x[7:4] + y[3:0];  // part-selects 

Function Calls

In the Function calls, the return value of a function is used immediately in an expression withaway presently correct now there the need of preliminary assigning it to a register or cable. It simply place the function call as one of the kind of operands.it is needful to generate sure you are belowstanding the bit width of the return value of function call.

Example  
Assign x = y & z & chk_yz(z, y); // chk_yz is a function 

. . ./* Definition of the function */ 
Function chk_yz; // function definition 
Input z,y; 
chk_yz = y^z; 
End function 

Modules

Module Declaration

In Verilog, A module is the principal style entity. This wislimdicates the name and slot list (arguments). The next couple of collections which specifies the input/away presently correct now thereput kind (input, away presently correct now thereput or inaway presently correct now there) and width of the every slot. The default slot width is only 1 bit. The slot variables must end up being declared simply by cable, wand,. . ., reg. The default slot variable is cable. Normally, inputs are cable end up beingcause their own own data is latched away presently correct now there’aspect the module. Outputs are of reg kind if their own own signals are stored inaspect.

Example

module sub_add(add, in1, in2, away presently correct now there); 
input add; // defaults to cable 
input [7:0] in1, in2; cable in1, in2; 

away presently correct now thereput [7:0] away presently correct now there; reg away presently correct now there; 
... statements ... 
End module 

Continuous Assignment

The continuous assignment in a Module is used for assigning a value on to a cable, which is the normal assignment used at away presently correct now there’aspect of always or preliminary blocks. This assignment is done with an explicit assign statement or to assign a value to a cable during it is declaration. Continuous assignment are continuously executed at the time of simulation. The order of assign statements does not affect it. If you do any kind of alter in any kind of of the appropriate-hand-aspect inputs signal it will alter a left-hand-aspect away presently correct now thereput signal.

Example

Wire [1:0] x = 2’y01;   // assigned on declaration 
Assign y = c | d;       // using assign statement 
Assign d = a & b; 
/* the order of the assign statements does not matter. */ 

Module Instantiations

Module declarations are templates for creating workionual objects. Modules are immediateiated inaspect other modules, and every immediateiation is creating a single object from thead wear template. The other thanion is the top-level module which is it is own immediateiation. The module’s slots must to end up being complemented to those which are degoodd in the template. It is specified −

  • By name, using a dot “.template slot name (name of cable connected to slot)”. Or

  • By position, placing the slots in the exworkion same place in the slot lists of both of the template and the instance.

Example

MODULE DEFINITION 
Module and4 (x, y, z); 
Input [3:0] x, y; 
Output [3:0] z; 
Assign z = x | y; 
End module 

Behavioural Modelling & Timing in Verilog

Behavioral models in Verilog contain procedural statements, which manage the simulation and manipulate variables of the data kinds. These all statements are contained wislim the procedures. Each of the procedure has an workionivity flow associated with it.

During simulation of end up beinghavioral model, all the flows degoodd simply by the ‘always’ and ‘preliminary’ statements start with every other at simulation time ‘zero’. The preliminary statements are executed once, and the always statements are executed repetitively. In this particular particular model, the register variables a and b are preliminaryized to binary 1 and 0 respectively at simulation time ‘zero’. The preliminary statement is then comppermited and is not executed again during thead wear simulation operate. This preliminary statement is containing a end up beinggin-end block (furthermore calimmediateed a sequential block) of statements. In this particular particular end up beinggin-end kind block, a is preliminaryized preliminary followed simply by b.

Example of Behavioral Modeling

module end up beinghave; 
reg [1:0]a,b; 

preliminary 
end up beinggin 
   a = ’b1; 
   b = ’b0; 
end 

always 
end up beinggin 
   #50 a = ~a; 
end 

always 
end up beinggin 
   #100 b = ~b; 
end 
End module 

Procedural Assignments

Procedural assignments are for updating reg, integer, time, and memory variables. There is a substantial difference end up beingtween procedural assignment and continuous assignment as descriend up beingd end up beinglow −

Continuous assignments drive net variables and are evaluated and updated whenever an input operand alters value.

Procedural assignments update the value of register variables below the manage of the procedural flow constructs thead wear surround them.

The appropriate-hand aspect of a procedural assignment can end up being any kind of expression thead wear evaluates to a value. However, part-selects on the appropriate-hand aspect must have constant indices. The lefthand aspect indicates the variable thead wear receives the assignment from the appropriate-hand aspect. The left-hand aspect of a procedural assignment can consider one of the folloearng forms −

  • register, integer, real, or time variable − An assignment to the name reference of one of these data kinds.

  • bit-select of a register, integer, real, or time variable − An assignment to a single bit thead wear leaves the other bit is untouched.

  • part-select of a register, integer, real, or time variable − A part-select of 2 or more contiguous bit is thead wear leaves the rest of the bit is untouched. For the part-select form, only constant expressions are legal.

  • memory element − A single word of a memory. Note thead wear bit-selects and part-selects are unlawful on memory element references.

  • concatenation of any kind of of the above − A concatenation of any kind of of the previous four forms can end up being specified, which effectively partitions the result of the appropriate-hand aspect expression and assigns the partition parts, in order, to the various parts of the concatenation.

Delay in Assignment (not for synthesis)

In a delayed assignment Δt time unit is comppermite end up beingfore the statement is executed and the lefthand assignment is made. With intra-assignment delay, the appropriate aspect is evaluated immediately but presently correct now there is a delay of Δt end up beingfore the result is place in the left hand assignment. If one more procedure alters a appropriate-hand aspect signal during Δt, it does not effect the away presently correct now thereput. Delays are not supsloted simply by synthesis tools.

Syntax

  • Procedural Assignmentvariable = expression

  • Delayed assignment#Δt variable = expression;

  • Intra-assignment delayvariable = #Δt expression;

Example

reg [6:0] sum; reg h, ziltch; 
sum[7] = b[7] ^ c[7]; // execute now. 
ziltch = #15 ckz&h; /* ckz&a evaluated now; ziltch alterd 
after 15 time unit is. */ 

#10 head wear = b&c; /* 10 unit is after ziltch alters, b&c is
evaluated and head wear alters. */ 

Bloccalifornia king Assignments

A bloccalifornia king procedural assignment statement must end up being executed end up beingfore the execution of the statements thead wear follow it in a sequential block. A bloccalifornia king procedural assignment statement does not prevent the execution of statements thead wear follow it in a parallel block.

Syntax

The syntax for a bloccalifornia king procedural assignment is as follows −

<lvalue> = <timing_manage> <expression>

Where, lvalue is a data kind thead wear is valid for a procedural assignment statement, = is the assignment operator, and timing manage is the optional intra – assignment delay. The timing manage delay can end up being possibly a delay manage (for example, #6) or an event manage (for example, @(podepressingvantage clk)). The expression is the appropriate-hand aspect value the simulator assigns to the left-hand aspect. The = assignment operator used simply by bloccalifornia king procedural assignments is furthermore used simply by procedural continuous assignments and continuous assignments.

Example

rega = 0; 
rega[3] = 1;            // a little-select 
rega[3:5] = 7;          // a part-select 
mema[adgown] = 8’hff;  // assignment to a memory element 
{carry, acc} = rega + regb;  // a concatenation 

Nonbloccalifornia king (RTL) Assignments

The non-bloccalifornia king procedural assignment permit is you to schedule assignments withaway presently correct now there bloccalifornia king the procedural flow. You can use the non-bloccalifornia king procedural statement whenever you like to generate a few register assignments wislim the exworkion same time step withaway presently correct now there regard to order or dependance upon every other.

Syntax

The syntax for a non-bloccalifornia king procedural assignment is as follows −

<lvalue> <= <timing_manage> <expression>

Where lvalue is a data kind thead wear is valid for a procedural assignment statement, <= is the non-bloccalifornia king assignment operator, and timing manage is the optional intra-assignment timing manage. The timing manage delay can end up being possibly a delay manage or an event manage (for example, @(podepressingvantage clk)). The expression is the appropriate-hand aspect value the simulator assigns to the left-hand aspect. The non-bloccalifornia king assignment operator is the exworkion same operator the simulator uses for the less-than-orequal relational operator. The simulator interprets the <= operator to end up being a relational operator when you use it in an expression, and interprets the <= operator to end up being an assignment operator when you use it in a non-bloccalifornia king procedural assignment construct.

How the simulator evaluates non-bloccalifornia king procedural assignments When the simulator encounters a non-bloccalifornia king procedural assignment, the simulator evaluates and executes the non-bloccalifornia king procedural assignment in 2 steps as follows −

  • The simulator evaluates the appropriate-hand aspect and schedules the assignment of the brand new value to consider place at a time specified simply by a procedural timing manage. The simulator evaluates the appropriate-hand aspect and schedules the assignment of the brand new value to consider place at a time specified simply by a procedural timing manage.

  • At the end of the time step, in which the given delay has expired or the appropriate event has considern place, the simulator executes the assignment simply by assigning the value to the left-hand aspect.

Example

module evaluates2(away presently correct now there); 
away presently correct now thereput away presently correct now there; 
reg a, b, c; 
preliminary 

end up beinggin 
   a = 0; 
   b = 1; 
   c = 0; 
end 
always c = #5 ~c; 
always @(podepressingvantage c) 

end up beinggin 
   a <= b; 
   b <= a; 
end 
endmodule 

Conditions

The conditional statement (or if-else statement) is used to generate a decision as to whether a statement is executed or not.

Formally, the syntax is as follows −

<statement> 
::= if ( <expression> ) <statement_or_null> 
||= if ( <expression> ) <statement_or_null> 
   else <statement_or_null> 
<statement_or_null> 

::= <statement> 
||= ; 

The <expression> is evaluated; if it is true (thead wear is, has a non-zero belowstandn value), the preliminary statement executes. If it is false (has a zero value or the value is x or z), the preliminary statement does not execute. If presently correct now there is an else statement and <expression> is false, the else statement executes. Since, the numeric value of the if expression is checked for end up beinging zero, particular shortcuts are achievable.

For example, the folloearng 2 statements express the exworkion same logic −

if (expression) 
if (expression != 0) 

Since, the else part of an if-else is optional, presently correct now there can end up being confusion when an else is omitted from a nested if sequence. This is resolved simply by always associating the else with the shut upst previous if thead wear lacks an else.

Example

if (index > 0) 
if (rega > regb) 
   result = rega; 
   else // else apprests to preceding if 
   result = regb; 

If thead wear association is not exworkly whead wear you like, use a end up beinggin-end block statement 
to force the proper association 

if (index > 0) 
end up beinggin 

if (rega > regb) 
result = rega; 
end 
   else 
   result = regb; 

Construction of: if- else- if

The folloearng construction occurs so usually thead wear it is worth a short separate discussion.

Example

if (<expression>) 
   <statement> 
   else if (<expression>) 
   <statement> 
   else if (<expression>) 
   <statement> 
   else  
   <statement>

This sequence of if’s (belowstandn as an if-else-if construct) is the many kind of general way of writing a multi-way decision. The expressions are evaluated in order; if any kind of expression is true, the statement associated with it is executed, and this particular particular terminates the whole chain. Each statement is possibly a single statement or a block of statements.

The final else part of the if-else-if construct handles the ‘none of the above’ or default case where none of the other conditions was satisfied. Sometimes presently correct now there is no explicit workionion for the default; in thead wear case, the trailing else can end up being omitted or it can end up being used for error checcalifornia king to capture an not achievable condition.

Case Statement

The case statement is a special multi-way decision statement thead wear checks whether an expression complementes one of a numend up beingr of other expressions, and branches accordingly. The case statement is helpful for describing, for example, the decoding of a miharvestrocessor instruction. The case statement has the folloearng syntax −

Example

<statement> 
::= case ( <expression> ) <case_item>+ endcase 
||= casez ( <expression> ) <case_item>+ endcase 
||= casex ( <expression> ) <case_item>+ endcase 
<case_item> 
::= <expression> <,<expression>>* : <statement_or_null> 
||= default : <statement_or_null> 
||= default <statement_or_null> 

The case expressions are evaluated and compared in the exworkion order in which they are given. During the collectionar oceanrch, if one of the case item expressions complementes the expression in mother or fatherheses, then the statement associated with thead wear case item is executed. If all comparisons fail, and the default item is given, then the default item statement is executed. If the default statement is not given, and all of the comparisons fail, then none of the case item statements is executed.

Apart from syntax, the case statement differs from the multi-way if-else-if construct in 2 imslotant ways −

  • The conditional expressions in the if-else-if construct are more general than comparing one expression with a few others, as in the case statement.

  • The case statement provides a definitive result when presently correct now there are x and z values in an expression.

Looping Statements

There are four kinds of looping statements. They provide a means of manageling the execution of a statement zero, one, or more times.

  • forever continuously executes a statement.

  • repeat executes a statement a fixed numend up beingr of times.

  • while executes a statement until an expression end up beingcomes false. If the expression starts away presently correct now there false, the statement is not executed at all.

  • for manages execution of it is associated statement(s) simply by a three-step process, as follows −

    • Executes an assignment normally used to preliminaryize a variable thead wear manages the numend up beingr of loops executed

    • Evaluates an expression—if the result is zero, the for loop exit is, and if it is not zero, the for loop executes it is associated statement(s) and then performs step 3

    • Executes an assignment normally used to modify the value of the loopmanage variable, then repeats step 2

The folloearng are the syntax rules for the looping statements −

Example

<statement> 
::= forever <statement> 
||=forever 
end up beinggin 
   <statement>+ 
end  

<Statement> 
::= repeat ( <expression> ) <statement> 
||=repeat ( <expression> ) 
end up beinggin
   <statement>+ 
end  

<statement> 
::= while ( <expression> ) <statement> 
||=while ( <expression> ) 
end up beinggin 
   <statement>+ 
end  
<statement> 
::= for ( <assignment> ; <expression> ; <assignment> ) 
<statement> 
||=for ( <assignment> ; <expression> ; <assignment> ) 
end up beinggin 
   <statement>+ 
end

Delay Controls

Delay Control

The execution of a procedural statement can end up being delay-manageimmediateed simply by using the folloearng syntax −

<statement> 
::= <delay_manage> <statement_or_null> 
<delay_manage> 
::= # <NUMBER> 
||= # <identifier> 
||= # ( <mintypmax_expression> )

The folloearng example delays the execution of the assignment simply by 10 time unit is −

#10 rega = regb;

The next three examples provide an expression folloearng the numend up beingr sign (#). Execution of the assignment delays simply by the amount of simulation time specified simply by the value of the expression.

Event Control

The execution of a procedural statement can end up being synchronized with a value alter on a net or register, or the occurrence of a declared event, simply by using the folloearng event manage syntax −

Example

<statement> 
::= <event_manage> <statement_or_null> 

<event_manage> 
::= @ <identifier> 
||= @ ( <event_expression> ) 

<event_expression> 
::= <expression> 
||= podepressingvantage <SCALAR_EVENT_EXPRESSION> 
||= negadvantage <SCALAR_EVENT_EXPRESSION> 
||= <event_expression> <or <event_expression>> 

*<SCALAR_EVENT_EXPRESSION> is an expression thead wear resolves to a one bit value.

Value alters on nets and registers can end up being used as events to trigger the execution of a statement. This is belowstandn as detecting an implicit event. Verilog syntax furthermore permit is you to detect alter based on the immediateion of the alter—thead wear is, toward the value 1 (podepressingvantage) or toward the value 0 (negadvantage). The end up beinghaviour of podepressingvantage and negadvantage for unbelowstandn expression values is as follows −

  • a negadvantage is detected on the transition from 1 to unbelowstandn and from unbelowstandn to 0
  • a podepressingvantage is detected on the transition from 0 to unbelowstandn and from unbelowstandn to 1

Procedures: Always and Initial Blocks

All procedures in Verilog are specified wislim one of the folloearng four Blocks. 1) Initial blocks 2) Always blocks 3) Task 4) Function

The preliminary and always statements are enabimmediateed at the end up beingginning of simulation. The preliminary blocks executes only once and it is workionivity expires when the statement has compalloweed. In contrast, the always blocks executes repeatedly. It’s workionivity expires only when the simulation is terminated. There is no limit to the numend up beingr of preliminary and always blocks thead wear can end up being degoodd in a module. Tasks and functions are procedures thead wear are enabimmediateed from one or more places in other procedures.

Initial Blocks

The syntax for the preliminary statement is as follows −

<preliminary_statement> 
::= preliminary <statement>

The folloearng example illustrates the use of the preliminary statement for preliminaryization of variables at the start of simulation.

Initial 
Begin 
   Areg = 0; // preliminaryize a register 
   For (index = 0; index < dimension; index = index + 1) 
   Memory [index] = 0; //preliminaryize a memory 
   Word 
End

Another typical usage of the preliminary Blocks is specification of waveform descriptions thead wear execute once to provide stimulus to the main part of the circuit end up beinging simulated.

Initial 
Begin 
   Inputs = ’b000000; 
   // preliminaryize at time zero 
   #10 inputs = ’b011001; // preliminary pattern 
   #10 inputs = ’b011011; // 2nd pattern 
   #10 inputs = ’b011000; // third pattern 
   #10 inputs = ’b001000; // final pattern 
End 

Always Blocks

The ‘always’ statement repeats continuously throughaway presently correct now there the whole simulation operate. The syntax for the always statement is given end up beinglow

<always_statement> 
::= always <statement> 

The ‘always’ statement, end up beingcause of it is looping nature, is only helpful when used in conjunction with a couple of form of timing manage. If an ‘always’ statement provides no means for time to advance, the ‘always’ statement generates a simulation deadlock condition. The folloearng code, for example, generates an infinite zero-delay loop −

Always areg = ~areg; 

Providing a timing manage to the above code generates a achievablely helpful description—as in the folloearng example −

Always #half_period areg = ~areg; 
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